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Data Path Interface (DPI) to Utopia Level 2 Translation Device
IDT77V011
Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16-bit modes. Supports UTOPIA Level 2 Cell Level Handshake. Supports up to 31 PHYs on the UTOPIA Level 2 interface. Supports either 4-bit or 8-bit DPI interface. Supports cell sizes from 52 to 56 bytes on the DPI interface. Supports DPI operation up to 50MHz. Either Utility Bus or Parallel Manager Management interface for configuring and reading status of PHY registers. In-StreamTM (In-band) programming for configuration of device and management interface communications. TAG Routing for flexibility in routing cells. Single +3.3V 0.3V power supply required. Inputs are +5.0V tolerant.
By providing a smooth translation to the UTOPIA Level 2 multi-PHY interface, the IDT77V011 offers the opportunity to connect up to 31 PHY ports to a single 155Mbps port of the IDT77V400 Switching Memory. The IDT77V011 can also provide both transmit and receive TAG Routing, with each direction being individually programmed. In the receive direction up to four bytes can be added to the cell. In the transmit direction up to four bytes can be removed from the cell. This makes the IDT77V011, when combined with the IDT77V400, an ideal component for DSLAM and 25Mbps applications where the user would like to implement OC-3 bandwidth of a single IDT77V400 port to a number of lower bandwidth ports. The 77V011 utilizes In-StreamTM programming for its device configuration options. The cells are received on the DPI transmit interface, identified and sent to the internal cell interpreter for decoding and execution. In-StreamTM programming cells are transmitted based on a round-robin scheduler, which provides equal priority for each of the subports and the cell generator. This methodology is also used to communicate and configure the PHYs that are connected to the IDT77V011. Other features include an EEPROM that holds information for initialization and Discovery/Identify cells, and a Management interface to access the PHY devices.
The IDT77V011provides the interface translation between a 4 or 8-bit Data Path Interface (DPI) and an 8 or 16-bit UTOPIA Level 2 interface. DPI offers a reduced device pin count and gives the IDT77V400 Switching Memory a high degree of port configuration flexibility.
PDUJDL' NFRO% PDUJDL' NFRO% PDUJDL' NFRO% PDUJDL' NFRO%
QRLWSLUFVH' QRLWSLUFVH' QRLWSLUFVH' QRLWSLUFVH'
VHUXWDH)

.
UTOPIA 2 8/16-bit IDT77V011
DPI 4/8-bit IDT77V400 Switching Memory
.
ADSL PHY
ADSL PHY
ADSL PHY
.
Management Bus
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Figure 1 Typical IDT77011 ADSL DSLAM Application with the IDTV400 Switching Memory
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2001 Integrated Device Technology, Inc.
March 15, 2001
DSC 4308/8
IDT77V011
INDEX VCC TxDATA[11] TxDATA[10] TxDATA[9] TxDATA[8] TxDATA[7] TxDATA[6] TxDATA[5] GND VCC TxDATA[4] TxDATA[3] TxDATA[2] TxDATA[1] TxDATA[0] TxREF GND VCC DTxDATA[0] DTxDATA[1] DTxDATA[2] DTxDATA[3] DTxDATA[4] DTxDATA[5] DTxDATA[6] DTxDATA[7] DTxFRM GND DTxCLK VCC DRxCLK DRxFRM DRxDATA[0] DRxDATA[1] DRxDATA[2] GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
GND TxDATA[12] TxDATA[13] TxDATA[14] TxDATA[15] TxPRTY T EN B TxLED VCC GND TSOC TxADDR[4] TxADDR[3] TxADDR[2] TxADDR[1] TxADDR[0] TCLK GND TCLAV REFCLK VCC GND RCLK RENB RxADDR[0] RxADDR[1] RxADDR[2] RxADDR[3] RxADDR[4] RxLED VCC GND RCLAV RSOC RxDATA[15] VCC
VCC DRxDATA[3] DRxDATA[4] DRxDATA[5] DRxDATA[6] DRxDATA[7] VCC GND SYSCLK S YSR ST EEDIN EEDOUT EECS EECLK GND CTRL_B CTRL_A VCC MBUS[11] MBUS[10] MBUS[9] MBUS[8] MBUS[7] MBUS[6] MBUS[5] GND MBUS[4] MBUS[3] MBUS[2] MBUS[1] MBUS[0] VCC MGMT[4] BMODE PHYINT GND
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
QRLWDUXJLIQR& QL3 QRLWDUXJLIQR& QL3 QRLWDUXJLIQR& QL3 QRLWDUXJLIQR& QL3
PDUJDL' NFRO% PDUJDL' NFRO% PDUJDL' NFRO% PDUJDL' NFRO%
DPI Transmit Interface TAG & Port Address Removal UTOPIA II Transmit Interface Cell Generator EEPROM Interface Cell Receiver Management Interface DPI Receive Interface TAG & Port Address Adder UTOPIA II Receive Interface
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IDT77V011 PQFP TOP VIEW3
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
GND RxDATA[14] RxDATA[13] RxDATA[12] RxDATA[11] RxDATA[10] RxDATA[9] RxDATA[8] VCC GND RxDATA[7] RxDATA[6] RxDATA[5] RxDATA[4] RxDATA[3] RxDATA[2] RxDATA[1] RxDATA[0] VCC GND MDATA[7] MDATA[6] MDATA[5] MDATA[4] MDATA[3] MDATA[2] MDATA[1] MDATA[0] VCC GND MGMT[5] MGMT[1] MGMT[2] MGMT[3] PHY RST VCC
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1. All power pins must be connected to a 3.3V 0.3V power supply. 2. All GND pins must be connected to ground supply. 3.
This text does not indicate orientation of the actual part-marking.
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IDT77V011
DTxDATA [0] DTxDATA [1] DTxDATA [2] DTxDATA [3] DTxDATA [4] DTxDATA [5] DTxDATA [6] DTxDATA [7] DTxFRM DTxCLK
19
I
Normal
4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0]. 4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0]. 4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0]. 4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0]. 4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0]. 4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0]. 4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0]. 4-bit or 8-bit input data bus used to transfer data from a DPI device. When in 4-bit mode use DTxDATA [3:0]. DPI Transmit Start of Frame Marker. Transmit DPI Clock. 4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0]. 4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0]. 4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0]. 4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0]. 4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0]. 4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0]. 4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0]. 4-bit or 8-bit output data bus used to transfer data to a DPI device. When in 4-bit mode use DRxDATA [3:0]. DPI Receive Start of Frame Marker. Receive DPI Clock. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0].
20 21 22 23 24 25 26 27 29 33 34 35 38 39 40 41 42 32 31 91 92 93 94 95 96 97 98 101 102
I I I I I I I I O O O O O O O O O O I/O I I I I I I I I I I
Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal
DRxDATA [0] DRxDATA [1] DRxDATA [2] DRxDATA [3] DRxDATA [4] DRxDATA [5] DRxDATA [6] DRxDATA [7] DRxFRM DRxCLK RxDATA [0] RxDATA [1] RxDATA [2] RxDATA [3] RxDATA [4] RxDATA [5] RxDATA [6] RxDATA [7] RxDATA [8] RxDATA [9]
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HOED7 QRLWSLUFVH' QL3 HOED7 QRLWSLUFVH' QL3 HOED7 QRLWSLUFVH' QL3 HOED7 QRLWSLUFVH' QL3
IDT77V011
RxDATA [10]
103
I
Normal
8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 input data bus used to transfer data from a PHY device. When in 8-bit mode use RxDATA [7:0]. UTOPIA 2 Receive Start of Cell marker. UTOPIA 2 Receive Cell Available. UTOPIA 2 Receive Enable. UTOPIA 2 Receive Address Bus. UTOPIA 2 Receive Address Bus. UTOPIA 2 Receive Address Bus. UTOPIA 2 Receive Address Bus. UTOPIA 2 Receive Address Bus. UTOPIA 2 Receive LED. UTOPIA 2 Receive Clock. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0].
RxDATA [11] RxDATA [12] RxDATA [13] RxDATA [14] RxDATA [15] RSOC RCLAV RENB RxADDR [0] RxADDR [1] RxADDR [2] RxADDR [3] RxADDR [4] RxLED RCLK TxDATA [0] TxDATA [1] TxDATA [2] TxDATA [3] TxDATA [4] TxDATA [5] TxDATA [6] TxDATA [7] TxDATA [8] TxDATA [9] TxDATA [10]
104 105 106 107 110 111 112 121 120 119 118 117 116 115 122 15 14 13 12 11 8 7 6 5 4 3
I I I I I I I O O O O O O O O O O O O O O O O O O O
Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal
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IDT77V011
TxDATA [11] TxDATA [12] TxDATA [13] TxDATA [14] TxDATA [15] TSOC TCLAV TENB TxADDR[0]
2
O
Normal
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. 8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use TxDATA [7:0]. UTOPIA 2 Transmit Start of Cell marker. UTOPIA 2 Transmit Cell Available. UTOPIA 2 Transmit Enable. UTOPIA 2 Transmit Address Bus [LSB]. Subport Byte Location. Indicates what byte the Tx and Rx Subport Address is located in [LSB]. UTOPIA 2 Transmit Address Bus [LSB+1]. Subport Byte Location. Indicates what byte the Tx and Rx Subport Address is located in [LSB+1]. UTOPIA 2 Transmit Address Bus [LSB+2]. Subport Byte Location. Indicates what byte the Tx and Rx Subport Address is located in [MSB]. UTOPIA 2 Transmit Address Bus [LSB+3]. Initialize from EEPROM. Selects whether five bytes of EEPROM are to be written to In-StreamTM Cell Header and In-StreamTM Subport. "0" do not write five byte value, "1" write five byte value from EEPROM. UTOPIA 2 Transmit Address Bus [MSB]. UTOPIA 2 Transmit LED. UTOPIA 2 Transmit Clock. Parity for DTxDATA [15:0]. 8 KHz reference clock used to generate TxREF. 8KHz reference clock used by PHY. EEPROM Clock. EEPROM Chip Select. Serial Input from the EEPROM. Serial Output to the EEPROM. Bus Mode. Selects Motorola or Intel bus mode. "0" selects Motorola, "1" selects Intel.
143 142 141 140 134 126 138 129
O O O O O I O O I
Normal Normal Normal Normal Normal Normal Normal Normal Reset Normal Reset Normal Reset Normal Reset Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal
TxADDR[1]
130
O I
TxADDR[2]
131
O I
TxADDR[3]
132
O I
TxADDR[4] TxLED TCLK TxPRTY REFCLK TxREF EECLK EECS EEDIN EEDOUT BMODE MBUS[0]
133 137 128 139 125 16 50 49 47 48 70 67
O O O O I O O O I O I O
UTOPIA 2 Address Bus. Upper 64 bytes used for 32 address pointers describing PHY's. Utility Bus Utility bus PHY chip select (CS[1]).
I MBUS[1] 66 O
Reset
TxSIZE[0] - Number of bytes to remove from cell in transmit direction (LSB).
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's. Utility Bus Utility bus PHY chip select (CS[2]).
I
Reset
TxSIZE[1] - number of bytes to remove from cell in transmit direction (LSB + 1).
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IDT77V011
MBUS[2]
65
O
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[3]). I MBUS[3] 64 O Reset TxSIZE[2] - number of bytes to remove from cell in transmit direction (MSB).
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's. Utility Bus Utility bus PHY chip select (CS[4]).
I MBUS[4] 63 O
Reset
TxLOC - Location of Tx TAG in cell. "0" TAG located at beginning of cell, "1" TAG located at end of cell.
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's. Utility Bus Utility bus PHY chip select (CS[5]).
I MBUS[5] 61 O
Reset
TxHEC - Add HEC placeholder. "0" do not add placeholder, "1" add placeholder.
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's. Utility Bus Utility bus PHY chip select (CS[6]).
I MBUS[6] 60 O
Reset
RxSIZE[0] - Number of bytes to add to cell in the receive direction (LSB).
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's. Utility Bus Utility bus PHY chip select (CS[7]).
I MBUS[7] 59 O
Reset
RxSIZE[1] - Number of bytes to add to cell in the receive direction (LSB + 1).
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's. Utility Bus Utility bus PHY chip select (CS[8]).
I MBUS[8] 58 O
Reset
RxSIZE[2] - Number of bytes to add to cell in the receive direction (MSB).
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's. Utility Bus Utility bus PHY chip select (CS[9]).
I MBUS[9] 57 O
Reset
RxLOC - Location of TAG in cell in the receive direction. RxLOC = "0" TAG located at beginning of cell, TxLOC = "1" TAG located at end of cell.
UTOPIA 2 Address bus (LSB+9). Utility Bus Utility bus PHY chip select (CS[10]).
I MBUS[10] 56 O
Reset
RxHEC - Remove HEC from cell. "0" do not remove HEC, "1" remove HEC.
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's. Utility Bus Utility bus PHY chip select (CS[11]).
I MBUS[11] 55 O
Reset
DPI Bus Size. Indicates whether DPI transmit and receive bus is 4-bits or 8-bits wide. "0" 4-bit DPI bus, "1" 8-bit DPI bus.
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's. Utility Bus Utility bus PHY chip select (CS[12]).
I MDATA[0] 81 I/O
Reset
UTOPIA Bus Size. Indicates whether the UTOPIA transmit and receive data bus is 8-bits or 16-bits wide. "0" 8-bit UTOPIA bus, "1" 16-bit UTOPIA bus.
UTOPIA 2 Management interface data bus [LSB]. Utility Bus Utility Bus address and data bus [LSB].
MDATA[1]
82
I/O
UTOPIA 2 Management interface data bus [LSB+1]. Utility Bus Utility Bus address and data bus [LSB+1].
MDATA[2]
83
I/O
UTOPIA 2 Management interface data bus [LSB+2]. Utility Bus Utility Bus address and data bus [LSB+2].
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IDT77V011
MDATA[3]
84
I/O
UTOPIA 2 Management interface data bus [LSB+3]. Utility Bus Utility Bus address and data bus [LSB+3].
MDATA[4]
85
I/O
UTOPIA 2 Management interface data bus [LSB+4]. Utility Bus Utility Bus address and data bus [LSB+4].
MDATA[5]
86
I/O
UTOPIA 2 Management interface data bus [LSB+5]. Utility Bus Utility Bus address and data bus [LSB+5].
MDATA[6]
87
I/O
UTOPIA 2 Management interface data bus [LSB+6]. Utility Bus Utility Bus address and data bus [LSB+6].
MDATA[7]
88
I/O
UTOPIA 2 Management interface data bus [MSB]. Utility Bus Utility Bus address and data bus [MSB].
MGMT[1]
77
O
UTOPIA 2 Validates Read or Write operation on Management interface (SEL). Utility Bus Utility bus PHY Chip Select (CS[0]).
MGMT[2]
76
O
UTOPIA II Management interface Read or Data Strobe (RD/DS). Utility Bus Utility bus read (RD).
I MGMT[3] 75 O
Reset
MMODE - Selects what type of management mode interface to use. "0" selects Utility Bus style, "1" selects UTOPIA 2 style.
UTOPIA 2 Management interface Write or Read/Write (WR/RW). Utility Bus Utility bus Write (WR).
I MGMT[4] 69 I
Reset
MGMT[3] - Selects clock direction for DRxCLK. "0" DRxCLK is an output, "1" DRxCLK is an input.
UTOPIA 2 Management interface Ready or Data Acknowledge (RDY/DTACK). Utility Bus No functionality.
MGMT[5]
78
O
UTOPIA II No functionality. Utility Bus Utility Bus Address Latch Enable (ALE).
PHYRST PHYINT SYSRST SYSCLK CTRL_A CTRL_B Vcc
74 71 46 45 53 52
O I I I O O
Normal Normal Normal Normal Normal Normal Normal
PHY Reset. Resets the PHY device attached to the 77V011. PHY Interrupt. Phy layer interrupt with open drain active low output. System Reset. Resets the 77V011 and the PHY device(s) attached to it. System Clock. Control A for system engineering usage. This signal is Low after reset. Control B for system engineering usage. This signal is Low after reset. 3.3V Power supply pins.
1,10,18,30, Power 37,43,54,68, 73,80,90,100, 109,114,124, 136 9,17,28,36, Ground 44,51,62,72, 79,89,99,108, 113,123,127, 135,144
GND
Normal
Ground pins.
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IDT77V011
VCC VIN VOUT GND IOUT TSTG
3.3V Digital Supply Voltage Digital Input Voltage Digital Output Voltage Digital Ground Voltage Output Current Storage Temperature
GND-0.3 GND-0.3 GND-0.3 0 -- -55
3.6 5.50 VCC 0 12.0 140
V V V V mA C
VCC VIN TA titr titf VIH VIL
3.3V Digital Supply Voltage TTL Input Voltage Industrial Operating Temperature Input TTL rise time Input TTL fall time TTL Input High Voltage TTL Input Low Voltage
3.0 GND -40 -- -- 2.0 --
3.6 5.50 +85 2 2 -- 0.8
V V C ns ns V V
|ILI| |ILO| VOH VOL Icc
Input Leakage Current Output Leakage Current TTL Output High Voltage TTL Output Low Voltage Power Supply Current
VCC = 3.3V, VIN = 0V to VCC VOUT = 0V to VCC IOH = -4mA IOL = +4mA 155.52 Mbps
10 10 2.4 -- --
10 10 -- 0.4 110
A A V V mA
CIN COUT CBID
Input Capacitance Output Capacitance Bi-Directional Capacitance
All Inputs All Outputs All Bi-directional Pins
-- -- --
4 6 10
-- -- --
pF pF pF
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WLQ8
WLQ8
WLQ8
WLQ8 [D0
[D0
[D0
[D0 S\7
QL0
QL0
QL0 QL0 QRLWLGQR& QRLWLGQR&
VQRLWLGQR& JQLWDUHS2 GHGQHPPRFH5 VQRLWLGQR& JQLWDUHS2 GHGQHPPRFH5 VQRLWLGQR& JQLWDUHS2 GHGQHPPRFH5 VQRLWLGQR& JQLWDUHS2 GHGQHPPRFH5
UHWHPD UD3
UHWHPD UD3 UHWHPDUD3 UHWHPDUD3
VFLWVLUHWFDUDK& ODFLUWFHO( &' VFLWVLUHWFDUDK& ODFLUWFHO( &' VFLWVLUHWFDUDK& ODFLUWFHO( &'
VJQLWD5 PXPL[D0 HWXORVE$ VJQLWD5 PXPL[D0 HWXORVE$ VJQLWD5 PXPL[D0 HWXORVE$ VJQLWD5 PXPL[D0 HWXORVE$ HFQDWLFDSD& HFQDWLFDSD& HFQDWLFDSD& HFQDWLFDSD&
OREP\6 OREP\6 OREP\6 OREP\6
IDT77V011
The 77V011 uses a UTOPIA level 2 interface to receive and transmit ATM cells to and from the PHY device. It is a master UTOPIA interface and can operate with either an 8-bit or 16-bit data bus. Cell level handshake is used to transfer cells over the UTOPIA interface, byte level handshake is not supported. The Data Path Interface (DPI) can be used with a 4-bit or 8-bit data bus. The DPI receive interface can be programmed to operate with the clock as an input or output to accommodate either the IDT SWITCHStAR or a normal mode DPI device.
The EEPROM holds information for initialization and Discovery/Identify cells. The EEPROM is an optional device and does not need to be implemented. The Management interface contains the control pins used to access the internal PHY registers during normal operation, and to program the pin configurable registers at reset. The Misc. Interface contains two output test pins that can be controlled through the registers.
4-bit DPI 8-bit UTOPIA 2 DRxCLK DTxCLK RCLK TCLK SYSCLK SYSCLK/2
Table 1 Clock Relationship and Frequency
VKWGL: VX% $,3278 GQD ,3'
QLDPR' NFRO&
HFDIUHWQ, HFLYH' HFDIUHWQ, HFLYH' HFDIUHWQ, HFLYH' HFDIUHWQ, HFLYH'
DPI Receive Interface
DRxCLK DRxFRM DRxDATA[7:0]
RCLK RSOC RENB RxDATA[15:0] RCLAV RxADDR[4:0] IDT77V011 TCLK TxREF
DTxCLK
DPI Transmit Interface
UTOPIA Receive Interface
DTxFRM DTxDATA[7:0]
EEIN
TSOC T E NB TxDATA[15:0] TCLAV TxADDR[4:0] TxPRTY REFCLK
Serial EEPROM Interface
EEOUT EECS EECLK
UTOPIA Transmit Interface
System Interface
SYSRST SYSCLK
BMODE MBUS[11:0] MDATA[7:0] MGMT[1] MGMT[2] MGMT[3] MGMT[4] MGMT[5] P HYRST P H Y I NT
Misc. Interface
CNTRL_A CNTRL_B
Managment Interface
5348drw04
Figure 2 77V011 Interfaces
4-bit DPI 16-bit UTOPIA 2 SYSCLK SYSCLK/4
8-bit DPI 8-bit UTOPIA 2 SYSCLK SYSCLK
8-bit DPI 16-bit UTOPIA 2 SYSCLK SYSCLK/2
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March 15, 2001
IDT77V011
All clocks within the 77V011 are derived from the System Clock (SYSCLK). The frequency at which each output clock operates is dependent on the SYSCLK frequency and on the width of the DPI and UTOPIA 2 interfaces. See Clock Relationship Table for the relationship between SYSCLK and the output clocks. When DRxCLK is configured as an input it is totally asynchronous to SYSCLK. The DRxCLK clock domain within the 77V011 will run at the same frequency as the DRxCLK pin.
next sequential subport address once the cell transfer to a selected PHY port begins. When a PHY port responds with a high RCLAV during a cell transfer the 77V011 will continue to place the responding PHY subport address on the RxADDR[4:0] bus until the current cell transfer has ended and the responding PHY is given control of the bus. For example, if PHY 0x03 responds by asserting RCLAV while PHY 0x08 is still transferring a cell, then the 77V011 will continue to place PHY subport address 0x03 on the RxADDR[4:0] bus. This will continue until PHY 0x08 has finished its cell transfer and PHY 0x03 is given control of the receive bus. Polling will then resume with PHY subport address 0x04. A variance in the polling state machine may occur when DRxCLK is an input to the 77V011 and the frequency of DRxCLK is low enough to cause the UTOPIA receive bus to interrupt the cell transfer. The interruption will be indicated by RENB de-asserting high during the cell transfer. Data transfer will resume, where it left off, when RENB reasserts low. In order to resume the current cell transfer the same PHY subport address is placed on the RxADDR[4:0] bus one RCLK cycle before RENB is re-asserted low. Each time a cell transfer is interrupted the polling sequence is interrupted in this manner, which may happen frequently if DRxCLK is much slower than SYSCLK. For example if PHY port 0x03 is given control of the bus to transfer a cell. Once PHY port 0x03 takes control of the bus the 77V011 begins its polling sequence starting with PHY port 0x04. In the middle of the cell transfer data is halted by RENB de-asserting high, due to the DPI interface. At this time data transfer is halted while 77V011 is polling PHY port 0x08. After some period of time the DPI interface starts to transfer the remainder of the cell. The 77V011 puts the PHY subport address 0x03 on the RxADDR[4:0] bus and then asserts RENB low on the next RCLK cycle. Data transfer resumes where it had left off and the 77V011 starts polling the PHY ports starting at PHY subport address 0x09. In 8-bit UTOPIA mode there is a maximum one clock cycle delay between back to back cells when a TAG is not being used, and a maximum seven clock cycle delay when a four byte TAG is used. In 16bit mode there is a maximum one clock cycle delay between back to back cells when a TAG is not being used, and a maximum five clock cycle delay when a four byte TAG is used.
The 77V011 offers a fully compliant UTOPIA Level 2 receive interface, as specified by the UTOPIA Level 2 specification. The interface is a UTOPIA master and will operate with either an 8-bit or 16-bit Input Data Bus (RxDATA[15:0]). UTOPIA cell level handshake is used to receive ATM cells from the PHY device. The other signals associated with this interface are Receive Start of Cell (RSOC), Receive Enable (RENB), Receive Cell Available (RCLAV), Receive Clock (RCLK), Receive Address Bus (RxADDR[4:0]) and Receive LED (RxLED). The RxADDR[4:0] bus is fully UTOPIA Level 2 compliant and operates according to the MPHY Cell-Level Handshake with one RCLAV, as described in the UTOPIA Level 2 specification. RCLK is a continuous clock, whose relationship to SYSCLK is defined in the Clock Relationship and Frequency Table. RxLED indicates if there is activity on the RxDATA[15:0] bus. This signal asserts high when a cell is transferred over the bus and will stay high for 2 RCLK cycles. AT 40MHz this is approximately 0.1seconds.
22
When there is no cell transfer in progress, no PHY port is selected, the polling sequence is to output the Null PHY subport address (0x1F) on one RCLK cycle and then output a valid PHY subport address on the next RCLK cycle. This sequence is repeated starting at PHY port address 0x00 and ending at the value specified in Max Subports field. The 77v011 will wrap back to address 0x00 once it has polled the Max Subports address. A PHY device is selected when a PHY responds to its subport address by asserting RCLAV high. RENB will assert on the same RCLK cycle that RCLAV is asserted, assuming there is no valid cell transfer in progress. The 77V011 will resume polling starting with the
The 77V011 offers a fully compliant UTOPIA Level 2 transmit interface, as specified by the UTOPIA Level 2 specification. This is a master UTOPIA interface that uses UTOPIA cell level handshake to transmit ATM cells to the PHY device. It will operate with either a 8-bit or 16-bit Output Data Bus (TxDATA[15:0]). Other signals associated with this interface are Transmit Start of Cell (TSOC), Transmit Enable (TENB), Transmit Clock (TCLK), Transmit Cell Available (TCLAV), Transmit Reference Clock (TxREF), Reference Clock (REFCLK), Transmit Parity (TxPRTY), Transmit Address Bus (TxADDR[4:0]) and Transmit LED (TxLED). TCLK is a continuous clock, whose relationship is defined in the Clock Relationship and Frequency Table.
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UTOPIA transmit and receive bus size is selected at reset with the MBUS[11] signal. Setting MBUS[11] to a zero will select a 8-bit bus, while setting MBUS[11] to a one will select a 16-bit bus. The value of MBUS[11], at reset, is stored in the UTOPIA 2 Size bit of the Mode Select register. See the UTOPIA 2 Receive Register Table for register description. Polling on the UTOPIA 2 receive bus is done in a round robin fashion. The Max Subports field of the Configuration 2 register determines the upper boundary of the polled addresses. The default value of the Max Subports field is 0x1E, which is also the maximum valid PHY address. The user should not program a value of 0x1F, as this is defined as a Null PHY port by the UTOPIA 2 specification.
March 15, 2001
IDT77V011
TxREF is a 8KHz reference clock output generated from REFCLK. REFCLK is a 8KHz reference clock input used to generate the TxREF clock signal. TxLED indicates if there is activity on the transmit UTOPIA 2 bus. This signal asserts high when a cell is transferred over the bus, and will stay high for 2 TCLK cycles. AT 40MHz this is approximately 0.1 seconds.
22
output on the TxADDR[4:0] bus until another cell enters the 77V011 on the transmit DPI interface. When a cell is detected on the transmit DPI interface and a cell transfer is in progress on the transmit UTOPIA 2 interface, the subport is extracted and output on the TxADDR[4:0] bus, interleaved with the Null PHY subport address, to query the new PHY port. Once the current cell transfer on the transmit UTOPIA 2 interface is complete and the new PHY port has responded, the new cell will be transferred on the transmit UTOPIA 2 interface. With an 8-bit UTOPIA bus there is a maximum one clock cycle delay between back to back cells when switching is being done without a TAG, and there is a maximum five clock cycle delay if a four byte TAG is being used. There is a maximum three clock cycle delay between back to back cells in 16-bit UTOPIA mode without a TAG, and a maximum five clock cycle delay if a four byte TAG is being used. There are several registers associated with the UTOPIA 2 Transmit Interface. In-StreamTM programming cells are used to program the registers, which are described in the UTOPIA 2 Transmit Register Table.
TxPRTY is a parity bit for TxDATA[15:0] bus. The TxADDR[4:0] bus is fully UTOPIA Level 2 compliant and follows the MPHY Cell-Level Handshake with one TCLAV as described in the UTOPIA Level 2 specification. When a cell is transferred on the transmit DPI interface the subport address is analyzed and extracted by the 77V011. The subport address is then interleaved with the Null PHY subport address (0x1F) and output on the TxADDR[4:0] bus to query the corresponding PHY port. Upon detecting a high TCLAV the 77V011 will assert TENB low, TSOC and the first valid byte/word of data. The current PHY subport address will be
Mode Select
8006
2
UTOPIA 2 Size 0 - 1
Defined by pin Selects the size of the UTOPIA 2 transmit and receive data bus. "0" 8-bit UTOPIA 2 transmit and receive data bus, "1" 16-bit UTOPIA 2 transmit and receive data bus.
Table 2 UTOPIA 2 Receive Register Table
RCLK (output) RxADDR[4:0] (output) 1F 1 1F 2 1F 3 1F 1F 1B 1F 1C 1F
RCLAV (input) RENB (output) RSOC (input) RxDATA[7:0] (input)
1E
1
2
3
1A
1B
Figure 3 Polling Sequence with no Cell Transfer in Progress
RCLK (output) RxADDR[4:0] (output) RCLAV (input) RENB (output) RSOC (input) RxDATA[7:0] (input) 5 6 47 48 49 50 51 52 53 1 1F 1F 5 1F 6 1F 6 1F 7 1F 8
1
4
5
6
6
Figure 4 Polling Sequence with Cell Transfer in Progress 11 of 43 March 15, 2001
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TCLK (output) TxADDR[4:0] (output) TCLAV (input) TENB (output) TSOC (output) TxDATA[7:0] (output) 0 1 46 47 48 49 50 51 . 5348drw07 1B 1F 1B 1F 1B 1F 1B 1F 1B 1F 1B
Figure 5 Single Cell Transfer with no Cell Transfer in Progress
TCLK (output) TxADDR[4:0] (output) TCLAV (input) TENB (output) TSOC (output) TxDATA[7:0] (output) 47 48 49 50 51 52 53 1 2
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1F
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1B
Figure 6 Back-to-Back Cell Transfer on transmit UTOPIA 2 Bus
Configuration 1 Configuration 2
8001 8002
0 [1:0]
Drop Tx Cell Stall Tx
0-1 0x2
0 0x0
Drop a cell with an invalid subport address. "0" do not drop the cell, "1" drop the cell. Selects whether or not to stall the pipeline if the PHY transmit FIFO is full. "0" drop cell, "1" stall pipeline indefinitely, "2" stall pipeline for Stall Cycles. Indicates the maximum subport address value for the PHY(s) connected to the transmit UTOPIA 2 interface. Number of TCLK cycles the interface has to stall the pipeline when the PHY transmit FIFO is full. This field is valid only if the Stall Tx for Stall Cycles option is selected. Indicates if any cells have been dropped at the transmit UTOPIA 2 interface. This is a status indicator for the Stall Tx bit of the Configuration 2 register. "0" no cells have been dropped, "1" a cell was dropped because the PHY did not respond.
[6:2] Configuration 3 8003 [7:0]
Max Subports Stall Tx Cycles
0x00 - 0x1E 0x00 - 0xFF
0x1E 0xFF
Status
8009
2
Tx Cell Dropped
0-1
0
Table 3 UTOPIA 2 Receive Register Table
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The DPI Receive Interface is used to transfer cells from the 77V011 to the IDT SWITCHStAR or other DPI device. It supports either a 4-bit or 8-bit Output Data Bus (DRxDATA[7:0]) and follows the standard DPI timing characteristics as described in the DPI specification. Other signals associated with this interface are DPI Receive Start of Frame (DRxFRM), and DPI Receive Clock (DRxCLK). DRxCLK operates at a frequency less than or equal to SYSCLK. Depending on the DPI mode selected this clock will be either an input or an output. In Normal Mode DRxCLK is an input to the 77V011, and its frequency must be less than or equal to SYSCLK. In Switch Mode DRxCLK is a continuous clock generated by the 77V011, with its frequency being equal to SYSCLK. There is no flow control in Switch mode, as it is assumed that the IDT SWITCHStAR will be able to accept all incoming cells (non-blocking). Programming the clock direction is done at reset. The DPI mode is selected with the MGMT[3] signal at reset, with the condition of MGMT[3] being stored in the DPI Mode bit of the Mode Select register. Setting MGMT[3] ="0" selects Switch Mode (output), while setting MGMT[3] ="1" selects Normal Mode (input). The DPI bus size is selected with the MBUS[10] pin at reset, with the condition of MBUS[10] being stored in the DPI Size bit of the Mode
The DPI Transmit Interface is used to transfer cells from the IDT SWITCHStAR or other DPI device to the 77V011. It supports either a 4bit or 8-bit Input Data Bus (DTxDATA[7:0]) and follows the standard DPI timing characteristics as described in the DPI specification. Other signals associated with this interface are DPI Transmit Start of Frame (DTxFRM) and DPI Transmit Clock (DTxCLK). DTxCLK operates at a frequency equal to SYSCLK. DTxCLK can be stopped to control data flow to the PHY device. DTxFRM is the start of frame marker. This signal is one DTxCLK cycle long and is asserted high one DTxCLK cycle before the first valid nibble/byte of data.
Byte swapping must be performed to convert the 8 or 16-bit transmit and receive of the UTOPIA interface to the 4 or 8-bit transmit and receive of the DPI interface. In 4-bit DPI mode cell formatting is big endian, or upper nibble first, while in 8-bit DPI mode cell formatting is done little endian to match the IDT 77V400 Switching Memory. The UTOPIA to DPI Conversion Table illustrates how the 77V011 performs cell formatting in 4 and 8-bit DPI mode.
Mode Select
8006
0 1
DPI Size DPI Mode
0-1 0-1
Defined by pin Selects the size of DPI data bus. "0" 4-bit DPI transmit and receive data bus, "1" 8-bit DPI transmit and receive data bus. Defined by pin Selects DRxCLK direction. "0" switch mode (output), "1" normal mode (input).
Table 4 UTOPIA 2 Receive Register Table
DRxCLK (input/ output) DRxFRM (output) DRxDATA[3:0] (output) 0 1 2 3 103 104 105
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Figure 7 Nibble Mode One Cell Transfer on Receive DPI Bus 13 of 43 March 15, 2001
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The Data Path Interface (DPI) is a synchronous bus interface designed to transfer ATM cells between two devices. The 77V011 DPI interface will support either a 4-bit wide data bus (DPI-4) or an 8-bit wide data bus (DPI-8). There are separate transmit and receive interfaces, with all signals being sampled on the rising edge of their respective clock.
Select register. Setting MBUS[10] ="0" selects a 4-bit data bus, while setting MBUS[10] ="1" selects an 8-bit data bus. DRxFRM is the start of frame marker. This signal is one DRxCLK cycle long and is asserted high one DRxCLK cycle before the first nibble/byte of valid data.
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DRxCLK (input/ output) DRxFRM (output) DRxDATA[3:0] (output) 104 105 0 1 2 3 103 104 105 0
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Figure 8 Nibble Mode Back-to-Back Cell Transfer on Receive DPI Bus
DTxCLK (output) DTxFRM (input) DTxDATA[3:0] (input) 0 1 2 3 103 104 105
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Figure 9 Nibble Mode One Cell Transfer on Transmit DPI Bus
DTxCLK (output) DTxFRM (input) DTxDATA[3:0] 104 (input) 105 0 1 2 3 103 104 105 0
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Figure 10 Nibble Mode Back-to-Back Cell Transfer on Transmit DPI Bus
bit 7 GFC VPI[3:0] VPI[11:4] VPI[7:4] VPI[15:12]
bit 0
bit 3 GFC VPI[7:4] VPI[3:0]
bit 7 GFC VPI[3:0] VPI[11:4] VPI[7:4] VPI[15:12]
bit 0
bit 7 GFC VPI[3:0] VPI[11:8] VPI[7:4] VPI[15:12] VPI[7:4]
Figure 11 UTOPIA to DPI Conversion
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100ns, while the In-StreamTM (internal) reset command will keep the 77V011 in reset for 35 SYSCLK cycles. The 77V011 will remain in reset for 16 SYSCLK cycles after the deassertion of SYSRST, or the internal reset in the case of a Reset command. All outputs will be tri-stated starting two SYSCLK cycles after the assertion of SYSRST or the internal reset, and will stay tri-stated for 24 SYSCLK cycles after the deassertion of SYSRST or internal reset. The PHYRST pin will then assert low resetting the PHY devices for eight additional SYSCLK cycles. After the eight clock cycle period PHYRST pin will deassert high. Eight clock cycles may not be long enough to properly reset some PHY devices. In this case a pull down resistor should be connected to the PHYRST pin. This will allow the PHYRST pin to be asserted as soon as it is tri-stated, which will Lenten the time that the PHYRST pin is a logical zero. The PHY can be reset at any time by writing a one to the PHY Reset bit of the Reset register. Writing a one will force the external PHYRST pin low for 16 SYSCLK cycles. This register bit will return to zero once the reset command is completed. This method will only reset the PHY device connected to the PHYRST pin.
Pull-up or pull-down resistors must be connected to MBUS[11:0], MGMT[3:2] and TxADDR[3:0] signals, on the PCB, to select desired register values. The SYSRST signal must be asserted for at least one SYSCLK cycle to load the desired values. On the rising edge of SYSRST the 77V011 will begin loading the register values, which takes an additional 16 SYSCLK cycles. During this 16 clock cycle period all outputs will be tri-stated.
The 77V011 has the option to change the Read only pin configurable registers to Read/Write registers. Writing a one to the Override Pin Configuration bit of the Pin Controls register will change the pin configurable registers from Read only to Read/Write. This allows the 77V011 configuration parameters to be changed during normal operation. See Pin Configuration Table for register description.
The System Reset (SYSRST) pin or an In-StreamTM cell carrying the Reset command (Message Type ID 0x3) will reset the 77V011 and the PHY devices. The SYSRST pin must be asserted low for a minimum of
MBUS[2:0] MBUS[3] MBUS[4] MBUS[7:5] MBUS[8] MBUS[9] MBUS[10] MBUS[11] MGMT[2] MGMT[3] TxADDR[2:0]
Tx TAG Size Tx TAG Location Tx Add HEC Rx TAG Size Rx TAG Location Rx HEC DPI Size UTOPIA 2 Size MMODE DPI Mode Subport Byte Location
Number of bytes to remove from the cell. Valid values are from zero to four bytes.
Tx TAG [2:0]
Location of the transmit TAG. "0" transmit TAG located at the beginning of the cell, "1" trans- Tx TAG [4] mit TAG located at the end of the cell. Add a HEC placeholder to the cell. "0" do not add HEC placeholder, "1" add HEC placeholder. Tx TAG [3] Number of bytes to add to the cell. Valid values are from zero to four bytes. Rx TAG [2:0]
Location of the receive TAG. "0" receive TAG located at the beginning of the cell, "1" receive Rx TAG [4] TAG located at the end of the cell. Remove HEC byte from cell. "0" do not remove HEC byte, "1" remove HEC byte. Rx TAG [3]
DPI bus size. "0" 4-bit transmit and receive data bus, "1" 8-bit transmit and receive data bus. Mode Select [0] UTOPIA 2 bus size. "0" 8-bit transmit and receive data bus, "1" 16-bit transmit and receive data bus. Management mode. "0" Utility Bus style, "1" UTOPIA 2 style. DRxCLK direction. "0" switch mode (output), "1" normal mode (input). Mode Select [2] Mode Select [3] Mode Select [1]
Transmit and receive subport address location. Indicates what byte of the header the transmit Tx Subport Position and receive subport addresses are located in. Valid values are zero to three. [2:0] and Rx Subport Position [2:0] Five byte write from EEPROM to In-StreamTM Cell Header and In-StreamTM Subport registers Mode Select [4] at reset. "0" do not write five byte value, "1" write five byte value. Table 5 Reset Configuration Pins
TxADDR[3]
Init from EEPROM
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The 77V011 can run at a maximum SYSCLK speed of 50MHz. The DPI clocks must run at 40MHz, or greater, to achieve 155.52Mbps data rate with overhead. The Clock Speed vs. Bandwidth Table lists some of the possible data rates and the clock frequencies required to achieve them.
IDT77V011
Pin Controls
801A
0
Override Pin Configuration
0-1
0
Enables writing to pin configurable registers during normal operation. "0" pin configurable registers are read only, "1" pin configurable registers are read/write registers
Table 6 Pin Configuration Table
Software Reset (In-StreamTM) SYSRST (external pin) PHYRST (register bit)
X X
X X X
Table 7 Reset Table
Calculated Bandwidth of UTOPIA Interface (cell rate in Mbps)
32 40 50 16 25 33 32 50
4 4 4 8 8 8 8 8
32 40 50 16 25 33 32 50
8 8 8 8 8 8 16 16
16 20 25 16 25 33 16 25
125.6 157 196.3 125.6 196.3 259.1 242.3 378.6
113.8 142.2 177.8 113.8 177.8 234.7 235 367.2
Table 8 Clock Speed verses Bandwidth Table
(I)
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(O)
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(O)
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tPPHY tALR tRDPW
(O)
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tAAL
tALA Address Read Data from PHY tDRS tDRH
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Figure 12 Utility Bus Read Operation
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The Management interface is a multi-function interface used to read and write to the PHY registers during normal operation, and to configure the pin configurable registers during reset. Signals associated with the Management Interface are Bus Mode (BMODE), Management Bus (MBUS[11:0]), Management Data Bus (MDATA[7:0]), Management 1 (MGMT[1]), Management 2 (MGMT[2]), Management 3 (MGMT[3]), Management 4 (MGMT[4]), Management 5 (MGMT[5]), PHY Reset (PHYRST) and PHY Interrupt (PHYINT). During normal operation the Management Interface is used to access the PHY registers. The 77V011 will operate in either a Utility Bus mode or the Management Mode described in the UTOPIA 2 mode section A2.4.2 of the UTOPIA Level 2 specification. Refer to the Address Map for addressing description of the PHY registers.
MGMT[3] is an active low Write Enable (WR) used as an enable to write data to an addressed location on MDATA[7:0]. MGMT[5] is an active high Address Latch Enable (ALE) used to latch the address in the address phase of a Utility Bus read or write command. PHYRST is an active low PHY reset signal. PHYRST can be asserted by writing to the PHY Reset bit in the PHY Reset register. PHYINT is an active low interrupt signal. This signal is driven by the PHY layer and indicates that an interrupt has occurred. The interrupt must be cleared by the controlling CPU before another interrupt event can be reported. Registers associated with the management interface are described in the Management RegisterTable.
The Utility Bus is used to access and configure the PHY registers. Read and write commands are sent to the PHY with In-StreamTM programming cells. MBUS[11:0] are active low Chip Select Enable (CS[12:1]) signals used to select a particular PHY device. These are active low signals used to validate read, write, or addressing operations on the Utility Bus. MDATA[7:0] is a multiplexed byte wide address and data bus (AD[7:0]) used to address, read and write data on the Utility Bus.
A Utility bus read is initiated by an In-StreamTM programming cell. Once the 77V011 interprets the cell as a read command it will drive PHYCS, ALE, RD, and AD[7:0]. The PHY samples the address on the falling edge of ALE. Once PHYCS and RD assert the bus tristates and switches to an input for the PHY to place data on. The PHY drives the bus until the rising edge of PHYCS or RD. One Utility Bus read can include up to 32 bytes of data.
MGMT[1] is an active low Chip Select Enable (CS[0]) signal used to validate read, write, or addressing operations on the Utility Bus. MGMT[2] is an active low Read Enable (RD) used as an enable to read data from an addressed location on MDATA[7:0].
A Utility bus write is initiated by an In-StreamTM programming cell. Once the 77V011 interprets the cell as a write command it will drive PHYCS, ALE, WR, and AD[7:0]. The PHY samples the address on the falling edge of ALE. Once PHYCS and WR assert the 77V011 will write data to the PHY. One Utility Bus write can include up to 32 bytes of data.
(I)
SYSCLK tPALE tALPW
(O) (O) (O)
ALE PHYCS WR tAAL tPPHY tWRPW tALW tAW tALA Address Write Data to PHY tDWS tDWH
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Figure 13 Utility Bus Write Operation
Mode Select 8006 PHY Reset 8007
3 0
UTOPIA Manage- 0 - 1 ment Mode PHY Reset 0-1
Defined by pin Selects type of management interface to use. "0" Utility bus style, "1" UTOPIA 2 management style. 0 PHY Reset. "0" do not reset the PHY device, "1" reset the PHY device (PHYRST signal will be asserted low for at least 16 SYSCLK cycles).
Table 9 Pin Configuration Table 17 of 43 March 15, 2001
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IDT77V011
The UTOPIA 2 Management interface is used to access and configure the PHY registers. Read and write commands are sent to the PHY with In-StreamTM programming cells. BMODE selects the type of UTOPIA 2 Management Mode interface to be used as defined by the UTOPIA Level 2 specification. Setting BMODE ="0" selects the Motorola style, while setting BMODE ="1" selects the Intel mode. MBUS[11:0] are address bits in this mode and are used to access the internal registers of a particular PHY device. The addressing scheme of what PHY and register address is user definable. An example would be to use the upper five bits (MBUS[11:7]) for the subport number and the lower seven bits (MBUS[6:0]) for the PHY register address. MDATA[7:0] is a byte wide bi-directional data bus used to read data from or write data to a PHY device. MGMT[2] is an active low signal used as an enable to read data from the addressed location on the data bus when BMODE = "1", and when BMODE = "0" it is an active low enable used to read data from the PHY layer, or strobe write data to the PHY. MGMT[3] is an active low write enable used to write data to an addressed location when BMODE = "1", and when BMODE = "0" it defines the current transaction as a read, if equal to one, or a write, if equal to zero. MGMT[4] is an active low signal that indicates when a transfer on the MDATA[7:0] bus is complete. PHYRST is an active low PHY reset signal. PHYRST can also be asserted by writing to the PHY Reset bit in the PHY Reset register.
PHYINT is an active low interrupt signal. This signal is driven by the PHY layer and indicates that an interrupt has occurred. The interrupt must be cleared by the controlling CPU before another interrupt event can be reported. Registers associated with the management interface are described in the Management Register Table.
A read is initiated by the 77V011 driving the Address bus (MBUS[0:11]), asserting SEL (MGMT1) = "0" and asserting the appropriate strobe, which is dependant on the condition of BMODE. The PHY then drives RDY/DTACK (MGMT[4]) and the Data bus (MDATA[0:7]). The PHY will de-assert RDY/DTACK to signal the completion of the data cycle. When BMODE = "1" the data is strobed by asserting RD/DS, (MGMT[2]) = "0", with the WR/RW, (MGMT[3]) = "1". When BMODE = "0" the data is strobed by setting the WR/RW and RD/DS = "1".
A write is initiated by the 77V011 driving Address bus (MBUS[0:11]), the Data (MDATA[0:7]), and asserting the appropriate strobe. The PHY will drive RDY/DTACK (MGMT[4]) to specify the beginning and end of the cycle. When BMODE = "1" the data is strobed setting WR/RW (MGMT[3]) and RD/DS (MGMT[2]) = "1". When BMODE = "0" the data is strobed by setting RD/DS = "1" and setting WR/RW = "0".
(O) ADDR[11:0] tADRS (O) SEL tSERS (I/O) DATA[7:0] tDARV tADRH tRDPW tSELRH (O) WR/RW tRDYRV (I) RDY/DTACK (O) tRDYRT tDARIV
BMODE = "1"
(O)
RD/DS
RD/DS WR/RW
BMODE = "0"
(O)
(I) RDY/DTACK
5348drw1
Figure 14 UTOPIA 2 Parallel Interface Read Cycle 18 of 43 March 15, 2001
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HGR0 WQHPHJDQD0 $,3278 HGR0 WQHPHJDQD0 $,3278 HGR0 WQHPHJDQD0 $,3278 HGR0 WQHPHJDQD0 $,3278
IDT77V011
(O) ADDR[11:0] tADWS (O) SEL tSEWS (I/O) DATA[7:0] tDAWS tDAWH tSELWH (O) RD/DS tRDYWV (I) RDY/DTACK (O) (O) RD/DS WR/RW tRDYWT tWRPW WR/RW
BMODE = "0"
BMODE = "1"
(O)
(I) RDY/DTACK
5348drw1
Figure 15 UTOPIA 2 Parallel Interface Write Cycle
BMODE MBUS[0] MBUS[1] MBUS[2] MBUS[3] MBUS[4] MBUS[5] MBUS[6] MBUS[7] MBUS[8] MBUS[9] MBUS[10] MBUS[11] MDATA[7:0] MGMT[1] MGMT[2] MGMT[3] MGMT[4]
-- Tx TAG Size[0] Tx TAG Size[1] Tx TAG Size[2] TxLOC TxHEC Rx TAG Size[0] Rx TAG Size [1] Rx TAG Size [2] RxLOC RxHEC DPI_SEL UTOPIA_SEL -- -- MMODE DPI_MODE --
-- CS[1] CS[2] CS[3] CS[4] CS[5] CS[6] CS[7] CS[8] CS[9] CS[10] CS[11] CS[12] ADD/DATA[7:0] CS[0] RD WR --
BMODE ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] ADDR[8] ADDR[9] ADDR[10] ADDR[11] DATA[7:0] SEL RD/DS WR/RW RDY/DTACK
Table 10 Multiplexed Management Interface (Part 1 of 2)
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IDT77V011
MGMT[5] PHYRST PHYINT
-- -- --
ALE PHYRST PHYINT
-- PHYRST PHYINT
Table 10 Multiplexed Management Interface (Part 2 of 2)
MGMT[1] MBUS[11:0] MGMT[2] MGMT[3] MGMT[5] MDATA[7:0] PHYINT PHYRST
CS[0] CS[12:1] RD WR ALE ADDR/DATA[7:0] PHYINT PHYRST
O O O O O I/O I O
Chip Select[0]. Active low PHY chip select. Chip Select[12:1]. Active low PHY chip select for 12 additional PHYs connected to this device. Read Enable. Active low read enable. Write Enable. Active low write enable. Address Latch Enable. Active high address latch enable. Address/Data bus. Bidirectional address and data bus. PHY Interrupt. Active low PHY interrupt. PHY Reset. Active low PHY layer reset. Table 11 Utility Bus Management Interface
BMODE MBUS[11:0] MDATA[7:0] MGMT[1] MGMT[2]
BMODE ADDR[11:0] DATA[7:0] SEL RD/DS
I O I/O O O
Bus Mode. "0" selects Motorola management mode interface, "1" selects Intel management mode interface. Address bus used to select a register in a particular PHY device. Byte wide bidirectional data bus. Select. Active low signal used to validate ADDR[11:0] for a read or write operation. Read or Data Strobe. If BMODE = "0" then read data from the PHY layer, or strobe write data to the PHY layer. If BMODE ="1" then read data from the addressed location onto the DATA[7:0] bus. Write or Read/Write. If BMDOE ="0" then access is a read if high and a write if low. If BMODE ="1" then write data from DATA[7:0] to the addressed location. Ready or Data Acknowledge. Tri-stateable signal used to acknowledge the end of a transfer over DATA[7:0] bus. PHY Reset. Active low PHY layer reset. PHY Interrupt. PHY layer interrupt, with open-drain active low output. Table 12 UTOPIA 2 Management Interface
MGMT[3] MGMT[4] PHYRST PHYINT
WR/RW RDY/DTACK PHYRST PHYINT
O I O I
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IDT77V011
The EEPROM interface is an optional device that can be used for initialization and Discovery/Identify commands. The data is broken up into five fields. Bytes [4:0] contain a 5-byte value that can be read at reset and placed in the In-StreamTM Cell Header and In-StreamTM Subport registers. Bytes [3:0] are used for the In-StreamTM Cell Header registers, while byte [4] is used for the In-StreamTM Subport register. Bytes [7:5] are not used at this time, while bytes [39:8] contain 32-bytes of data, which is read when a Discovery/Identify command is encountered. Bytes [40:127] are reserved and bytes [128:255] are user defined. The registers associated with the EEPROM are listed in the EEPROM Register Table. Signals associated with this interface are Clock (EECLK), Chip Select (EECS), Data Out (EEDOUT), and Data In (EEDIN). EECLK is generated from SYSCLK and is an output of the 77V011. EECS is an active low chip select signal used to validate a read or write operation. EEDOUT is a serial data output pin to the EEPROM. EEIN is a serial input data pin from the EEPROM. At reset TxADDR[3] selects whether or not to write the first five bytes stored in the EEPROM to the In-StreamTM Cell Header and In-StreamTM Subport registers. Setting TxADDR[3] to a zero will select not to write the five byte value, while setting it to a one will write the value to the registers. The state of the TxADDR[3] signal, at reset, is stored in the Init from EEPROM bit of the Mode Select register. The EEPROM can be controlled with the EEPROM registers, which include Mux Select (EEPROM Mux Sel), Clock Out (EEPROM Clock Out), Chip Select (EEPROM Chip Select), Data Out (EEPROM Out), and Data In (EEPROM In). EEPROM Mux Select indicates whether the EEPROM pins will be connected to the internal logic, or to the EEPROM registers. When connected to the Internal logic 32-bytes of data are read from the EEPROM when a Discovery/Identify command is filtered. Controlling the EEPROM from the registers enables the user the flexibility of reading and writing the EEPROM at any time. Programming is accomplished with In-StreamTM cells regardless of the method used to access the EEPROM. EEPROM Clock Out is used to clock the EEPROM when it is being controlled by the registers. This register must be written to twice to execute one EEPROM clock cycle. You must write to the clock register to perform a read or write command. EEPROM Chip Select validates transactions on the EEPROM interface when being controlled by the EEPROM registers. EEPROM Out is a 1-bit register used to output data to the EEPROM. EEPROM In is a 1-bit register used to input data from the EEPROM.
A subport address is used to select a PHY port. The address can be up to five bits wide and be located anywhere in the first four bytes of the ATM cell, or first eight bytes of the cell if a four byte pre-pended TAG is being used. It can start in any bit location of a byte and can span over the byte boundary. The 77V011 uses the transmit subport field in determining how to route the cell. Normal cells have a PHY subport value from zero to the value stored in Max Subports bits of the Configuration 2 register. The Max Subport can be any value between zero and 30, as the UTOPIA 2 specification allows a total of 31 PHY ports to be connected to a UTOPIA 2 interface. The cell will be dropped if a subport greater than the Max Subports value is used. Once the subport field is read the 77V011 can replace the subport value with the value contained in the New Subport bits of the Modify Tx Subport register. Overwriting is determined by the Replace Subport bit of the Modify Tx Subport register. Only the data cells are affected when the 77V011 is configured to overwrite the subport field. The subport field of In-StreamTM cells are not altered. The Tx Byte Location bits of the Tx Subport Position register indicate what byte of the header the subport field starts in. Valid values are zero to three without using a TAG, and zero to seven when using a TAG. The subport field can start in any byte location of the header. This value is programmed at reset with TxADDR[2:0] pins. The 77V011 will concatenate the transmit subport field if any part of the subport field extends into the payload area of the cell. This is to ensure that the payload will not be altered. Bits [5:3] of the Tx Subport Position register contain the Tx Bit Location. This value indicates what bit in the byte the subport MSB is located in. A value of zero means that bit zero of the selected byte is MSB, bit 7 of the next byte is MSB-1, etc.... The subport can start on any bit of a byte and span multiple bytes. The number of bits to be used for the transmit subport field is programmed in the Tx Subport Width field bits of the Subport Configuration 1 register. The subport width can be any value between one and five, with the default value being five. A special mode of operation occurs when the Tx Subport Width is set to zero. When this is done, the cell will be passed to the transmit UTOPIA bus unchanged, and the polled address will be 0x0. This mode of operation is intended for system configurations with a single PHY device. Registers associated with the transmit cell routing are defined in the Transmit Cell Routing Register Table.
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IDT77V011
Byte 255
User Defined
128 127
Reserved
40 39
Discovery/Identify cell data
Reserved In-StreamTM Subport In-StreamTM Cell Header
8 7 5 4 3 0
5348drw17
Figure 16 EEPROM Memory Map
0xFFFFFF Reserved 0x008025 0x008024 0x008000 0x007FFF 0x000F00 0x000EFF 0x000E00 0x000DFF 0x000D00 0x000CFF 0x000C00 0x000BFF
77V011 Registers Reserved PHY #30 Registers PHY #29 Registers PHY #28 Registers
Aligned on byte boundary (8-bits = 1 byte)
PHY #2 Registers PHY #1 Registers PHY #0 Registers
0x000300 0x0002FF 0x000200 0x0001FF 0x000100 0x0000FF 0x000000
5348drw18
Figure 17 Register Address Map
22 of 43
March 15, 2001
IDT77V011
The receive cell routing is done by inserting the originating PHY port address into the receive subport address field. The 77V011 uses the subport field in determining how to route the cell. Normal cells have a PHY subport value from zero to the value stored in Max Subports bits of the Configuration 2 register. The Max Subport can be any value between zero and 30, as the UTOPIA 2 specification allows a total of 31 PHY ports to be connected to a UTOPIA 2 interface. In-StreamTM cells have a subport value that is defined in the InStreamTM Subport bits of the Subport Configuration 1 register. In order for In-StreamTM cells to be filtered properly two things must happen. First, the subport value within the received cell must match the InStreamTM Subport, Tx Subport Width, Tx Byte Location, and the Tx Bit Location register fields. Second, the received cell's header, excluding the PT, CLP and HEC fields, must match the In-StreamTM Cell Header register bits [31:4]. This dual check allows the In-StreamTM subport value to be the same as a valid PHY subport address. The Rx Byte Location bits of the Rx Subport Position register indicate what byte of the header the subport field starts in. Valid values are zero to three without using a TAG, and zero to seven when using a TAG. The subport field can start in any byte location of the header. This value is programmed at reset with TxADDR[2:0] pins. The 77V011 will concatenate the receive subport field if any part of the subport field extends into the payload area of the cell. This is to ensure that the payload will not be altered. Bits [5:3] of the Rx Subport Position register contain the Rx Bit Location. This value indicates what bit in the byte the subport MSB is located in. A value of zero means that bit zero of the selected byte is MSB, bit 7 of the next byte is MSB-1, etc.... The subport can start on any bit of a byte and span multiple bytes.
The number of bits to be used for the receive subport field is programmed in the Rx Subport Width field bits of the Subport Configuration 2 register. The subport width can be any value between one and five, with the default value being five. The Rx Out of Range Address Mask registers validate the VPI/VCI field, default value is 0x000000. This 24-bit value is used to compare against the incoming cell headers on the receive UTOPIA 2 interface. A bit wise AND operation is done between each bit of the incoming cell header and its corresponding bit of the Rx Out of Range Address Mask register. The Address Range Error bit of the Status register will be set to a one if the result of any of these AND operations is a one, indicating an invalid cell has been received. A Notification cell will be generated if the Rx Address Error bit of the Notification Mask register is set to a one. Another Notification cell will be generated 25ms after the error occurred if the Address Range Error bit has not been cleared. Additional Notification cells will be generated on 12ms intervals, thereafter, until the Address Range Error bit is cleared. The Rx Out of Range Subport bits of the Rx Out of Range Subport register stores the subport address of the violating Rx Out of Range cell. The CPU can read this register to determine what PHY port the invalid cell came from. The Rx Out of Range Subport bits will be overwritten when a new address range error occurs. Clearing the interrupt is done by writing a one to the Address Range Error bit of the Status register. Writing a one will clear the interrupt and reset the register bit to a zero. Registers associated with the receive cell routing are defined in the Receive Cell Routing Register Table.
Mode Select 8006
4
Init from EEPROM 0 - 1
Defined by pin Five byte write from EEPROM to In-StreamTM Cell Header and InStreamTM Subport registers at reset. "0" do not write five byte value, "1" write five byte value to registers. 0 Indicates if the EEPROM interface will be connected to the internal logic or the EEPROM registers. "0" connected to internal logic, "1" connected to EEPROM registers. EEPROM clock when EEPROM interface is connected to the EEPROM registers. "0" clock low, "1" clock high. EEPROM chip select when EEPROM interface is connected to the EEPROM registers. "0" EEPROM interface is selected, "1" EEPROM interface is not selected. EEPROM serial output when EEPROM interface is connected to the EEPROM registers. EEPROM serial input when EEPROM interface is connected to the EEPROM registers.
PIN Controls 801A
3
EEPROM Mux Select EEPROM Clock Out EEPROM Chip Select EEPROM Out EEPROM In
0-1
4 5
0-1 0-1
0 0
6 7
0-1 0-1
0 0
Table 13 Pin Configuration Table 23 of 43 March 15, 2001
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IDT77V011
In-StreamTM Subport DPI Tx
bits[4:0] of Subport Configuration Register
Replace Subport
bit5 of Modify Tx Subport Register
Mux
UTOPIA Tx
Cell Interpreter New Subport
bits[4:0] Modify Tx Subport Register
Process In-StreamTM Cell
5348drw19
Figure 18 Transmit Subport Interpreter
Register Content Max Subports Subport Width Replace Subport Bit Location Byte Location New Subport
0x1E 0x5 1 0x5 0x2 0x1F
In-StreamTM Subport 0x07 (matches bits[5:1] of In-StreamTM Cell Header byte 2 In-StreamTM Cell Header byte 3 0x00 In-StreamTM Cell Header byte 2 0xE0 In-StreamTM Cell Header byte 1 0x01 In-StreamTM Cell Header byte 0 0xF0
x = Any valid subport address
Normal Cell
Byte 0 52
0
1
2
3
4
5-52
DPI Tx (Incoming)
Bit 7 6 5 4 3 2 1 0 Bit 7 6
UTOPIA Tx (Outgoing)
5 4 3 2 1 0
x
x
x
x
x
1
1
1
1
1
Byte 0
In-stream Cell
0 1 2 3 4 5-52
52
DPI Tx (Incoming)
Bit
7 6 5 4 3 2 1 0
0
0
1
1
1
Filtered by Cell Interpreter
5348drw20
Figure 19 Example Subport Programming
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March 15, 2001
IDT77V011
A TAG can be added to the cell in either the transmit or receive direction. It can be up to four bytes long, and be added to the beginning or end of the cell. Programming a TAG for both the transmit and receive direction is done with external pins and internal registers, with each direction being individually programmed. Registers associated with the TAG are listed in the Transmit and Receive TAG Register Table.
A transmit TAG is programmed by first configuring the external pins and then programming the internal registers. The external pins are multiplexed with the MBUS[4:0] bus. The Copy EFCI bit, of the Configuration 1 register, selects whether or not to OR the EFCI bit of the cell header with the EFCI bit of the TAG area appended to the beginning of the cell, and place the OR'ed EFCI bit in the cell header. Setting this bit to zero will select not to OR the EFCI bits, while setting it to a one will OR the EFCI bits. This option is not valid when the TAG is appended to the end of the cell. Tx TAG Size [2:0] indicates the size of the TAG to be removed from the cell. This value is set with the MBUS[2:0] pins at reset and is stored in bits [2:0] of the Tx TAG register. Valid values for this field are zero to four. Tx TAG Location indicates whether the TAG is located at the beginning or end of the cell. Setting this bit to a zero indicates the TAG is located at the beginning of the cell, while setting this bit to a one indicates that the TAG is located at the end of the cell. This value is programmed at reset with the MBUS[3] pin and is stored in the Tx TAG Location bit of the Tx TAG register. Tx Add HEC indicates if a HEC placeholder should be added to the cell. Setting this bit to a zero indicates not to add the HEC byte, while setting it to a one indicates to add the HEC byte. This value is programmed at reset with the MBUS[4] pin and is stored in Tx ADD HEC bit of the Tx TAG register. The TAG 1, 2, 3 and 4 registers contain the header value used for the TAG. This value is only used for In-StreamTM cells. The default value is 0x000001FX, which can be changed by writing to the registers with InStreamTM cells. The Tx Move PT/CLP bit, of the Configuration 1 register, is an option to move the PT/CLP fields from the 4-byte TAG area appended to the beginning of the cell to the cell header. Setting this bit to a zero will not move the fields, while setting it to a one will move the PT/CLP fields. This option is not valid when the TAG is appended to the end of the cell. Registers associated with the Transmit TAG are listed in the Transmit TAG Register Table.
A TAG is added in the receive direction by first configuring the external pins and then programming the internal registers. The external pins are multiplexed with the MBUS[9:5] pins. The Rx TAG Size [2:0] indicates the size of the TAG to be appended. This value can be from zero to four and is set with the MBUS[7:5] pins at reset. This value is stored in Rx TAG Size bits of the Rx TAG register. The Rx TAG Location indicates whether the TAG is located at the beginning or end of the cell. Setting this bit to a zero indicates that the TAG is appended to the beginning of the cell, while setting this bit to a one indicates the TAG is appended to the end of the cell. This register bit is programmed at reset with the MBUS[8] pin and is stored in Rx TAG Location bit of the Rx TAG register. Rx Remove HEC is defined by pin MBUS[9] at reset and indicates whether the HEC byte should be removed or not. Setting this bit to zero will indicate not to remove the HEC byte, while setting it to a one will remove the HEC byte. This value is stored in the Rx Remove HEC bit of the Rx TAG register. The TAG 1, 2, 3 and 4 registers contain the header value used for the TAG. This value is only used for all cells. The default value is 0x000001FX, which can be changed by writing to the registers with InStreamTM cells. Rx Move PT/CLP bit, of the Configuration 1 register, is an option to move the PT and CLP fields of the ATM cell header into the four bytes of TAG area. Setting this bit to zero will not move these fields, while setting it to a one will move these fields from the incoming cell header to the TAG area. This enables a DPI device or SWITCHStAR that is switching on the TAG area to find OAM cells, do low priority cell discards and EFCI processing. This option is only valid if using all four bytes of TAG and switching is being done on the TAG appended to the beginning of the cell. This option is not valid when a TAG is appended to the end of the cell. Registers associated with the Receive TAG are listed in the Receive TAG Register Table.
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March 15, 2001
IDT77V011
Configuration 2
8002
[6:2] Max Subports [4:0] In-StreamTM Subport
0x00 - 0x1E 0x1E 0x00 - 0x1F 0x00 0x5
Indicates the maximum subport address for the PHY's connected to the transmit UTOPIA 2 interface. Subport address used to filter In-StreamTM programming cells. Programs how many bits will be used for subport addressing in the transmit direction. New value used to replace subport address in outgoing cells. This value will only be used if the Replace Subport bit of the Modify Tx Subport register is set to a one. Indicates whether or not to replace the subport address in outgoing cells. "0" do not replace the subport address, "1" replace the subport address with the value in the New Subport bits of the Modify Tx Subport register.
Subport Configuration 1
8013
[7:5] Tx Subport Width 0x0 - 0x7 Modify Tx Subport 8014 [4:0] New Subport
0x00 - 0x1F 0x00
5
Replace Subport 0x0 - 0x7
0
Tx Subport Position
8015
[2:0] Tx Byte Location 0x0 - 0x7 [5:3] Tx Bit Location 0x0 - 0x7
Defined by Indicates what byte of the transmit cell header the subport address starts pin in. The subport address can cross the byte boundary. 0x5 Indicates what bit of the byte defined by the Tx Byte Location bits of the Tx Subport Position register the MSB of the transmit subport address starts. The subport address can cross the byte boundary.
Table 14 Transmit Cell Routing Register Table
Notification Mask
8008
1
Rx Address Error 1 - 0
0
Mask Address Range Error notification. "0" no Event Notification cell will be generated when a Rx Out of Range Address Error occurs, "1" generate Event Notification cell when a Rx Out of Range Address Error occurs. Address Range Error indication when an Address Range Error occurs. "0" no Address Range Error detected, "1" Address Range Error has been detected. Indicates that a Address Error occurred more than 25ms ago, and Address Range error status bit has not been cleared. This bit will return to zero once the interrupt is cleared. "0" no Address Range Errors detected, "1" Address Range Error occurred more than 25ms ago and has not been cleared. The subport address of a cell containing an invalid cell header. Value used to validate cells on the receive UTOPIA interface. Value used to validate cells on the receive UTOPIA interface. Value used to validate cells on the receive UTOPIA interface. Programs how many bits will be used for subport addressing in the receive direction.
Status
8009
1
Address Range Error Address Error Status
1-0
0
Timeout Status
800A
1
1-0
0
Rx Out of Range Subport
800B
[4:0] Rx Out of Range 0x00 - 0x1F 0x00 Subport [7:0] Address Mask Register [23:16] [7:0] Address Mask Register [15:8] [7:0] Address Mask Register [7:0] 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x5
Rx Out of Range 801C Address Mask byte 2 Rx Out of Range 800D Address Mask byte 1 Rx Out of Range 800E Address Mask byte 0 Subport Configuration 2 Rx Subport Position 8023 8024
[2:0] Rx Subport Width 0x0 - 0x7 [2:0] Rx Byte Location 0x0 - 0x7 [5:3] Rx Bit Location 0x0 - 0x7
Defined by Indicates what byte of the receive cell header the subport starts in. The subport address can cross the byte boundary. pin 0x5 Indicates what bit of the byte defined by the Rx Byte Location bits of the Rx Subport Position register the MSB of the receive subport address starts. The subport address can cross the byte boundary.
Table 15 Receive Cell Routing Register Table
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HPD1 UHWVLJH5
IDT77V011
Configuration 1
8001
2
Rx Move PT/CLP
0-1
0
Selects whether or not to move the PT/CLP fields from the cell header into the 4-byte TAG area appended to the beginning of the cell. This option is not valid when the TAG is appended to the end of the cell. "0" do not move the PT/CLP to the 4-byte TAG area, "1" move the PT/CLP to the 4-byte TAG area. Number of bytes to add to ATM cell in the receive direction. Valid values are from zero to four. Remove HEC byte from cell. "0" do not remove the HEC byte from the cell, "1" remove the HEC byte from the cell. TAG location in receive direction. "0" receive TAG is located at the beginning of the cell, "1" receive TAG is located at the end of the cell. TAG added to cell. TAG added to cell. TAG added to cell. TAG added to cell.
Rx TAG
8005
[2:0] 3 4
Rx Tag Size [2:0] Rx Remove HEC Rx TAG Location TAG [31:24] TAG [23:16] TAG [17:8] TAG [7:0]
0-4 0-1 0-1 0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF
Defined by pin Defined by pin Defined by pin 0x00 0x00 0x00 0x00
TAG byte 3 TAG byte 2 TAG byte 1 TAG byte 0
8016 8017 8018 8019
[7:0] [7:0] [7:0] [7:0]
Table 16 Receive Tag Register Table
Configuration 1
8001
1
Copy EFCI
0-1
0
Selects whether or not to OR the EFCI bit of the cell header with the EFCI bit of the 4-byte TAG area appended to the beginning of the cell, and place the OR'ed EFCI bit in the cell header. This option is not valid when the TAG is appended to the end of the cell. "0" do not OR the EFCI bit to the 4-byte TAG area, "1" OR the EFCI bit to the 4-byte TAG area. Selects whether or not to move the PT/CLP fields from the 4-byte TAG area appended to the beginning of the cell into the cell header. This option is not valid when the TAG is appended to the end of the cell. "0" do not move the PT/CLP fields to the cell header, "1" move the PT/ CLP fields to the cell header. Number of bytes to remove from the ATM cell in the transmit direction. Valid values are from zero to four. Add a HEC placeholder in the transmit direction. "0" do not add a HEC placeholder, "1" add a HEC placeholder. TAG location in transmit direction. "0" transmit TAG is located at the beginning of the cell, "1" transmit TAG is located at the end of the cell.
3
Tx Move PT/CLP
0-1
0
Tx TAG
8004
[2:0] 3 4
Tx TAG Size Tx Add HEC Tx TAG Location
0x0 - 0x4 0-1 0-1
Defined by pin Defined by pin Defined by pin
Table 17 Transmit Tag Register Table
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HPD1 UHWVLJH5
HPD1 UHWVLJH5
IDT77V011
In-StreamTM programming cells are used to carry commands to the 77V011 and for the CPU to receive information from the 77V011. Cells are received on the DTxDATA[7:0] bus. All cells received on the DTxDATA[7:0] data bus are filtered by the cell interpreter to determine if they are In-StreamTM programming cells. In order to be recolonized InStreamTM programming cells have a unique cell header. The default value is 0x000001FX, which can be changed by writing to the InStreamTM Cell Header 1, 2, 3 and 4 registers, and have a subport value that matches the In-StreamTM Subport field of the Subport Configuration Register. All four In-StreamTM Cell Header registers can be written to in one four byte write with an In-StreamTM cell. The bytes are written MSB to LSB. The new cell header will be used for returning a Reply Notification cell, following the write operation. The 77V011 supports the following set of In-StreamTM functions, Discover/Identify, Reset, Register Read, Register Write, Event Notification and Reply Notification. The Discover/Identify command is sent by the CPU to the 77V011, and is used to either discover the 77V011 or to ensure that the 77V011 is still attached (heart beat). The Reset command is sent from the CPU to the 77V011, which indicates that the 77V011 must perform a hard reset and re-initialize itself to its default state. The Register Read command is used to read the value of one or more registers. Up to 31-bytes can be read with one In-StreamTM cell. The Register Write command is used to write a value to one or more registers. Up to 31-bytes can be written with one In-StreamTM cell. The Event Notification command is sent from the 77V011 to the CPU and indicates that an event has happened that requires CPU intervention. The Reply Notification command is sent from the 77V011 to the CPU in response to command cells sent by the CPU. The 77V011 will generate a Reply Notification response to a Discover/Identify, Register Read and Register Write command, but not for a Reset command. This option is enabled by setting the Acknowledge Request bit in the Message Type Field of the In-StreamTM command cell. The In-StreamTM cell format is broken up into six sections, which vary slightly depending on the type of command the cell caries. The first five bytes contain the cell header. The In-StreamTM programming cell address is in the first 28-bits with the default value of GFC =0x0, VPI =0x0, VCI =0x001F, PT/CLP =0xX, where X=don't care. The remaining byte is the HEC. Bytes six and seven of the cell contain the Transaction ID information. This field is two bytes wide and is used to correlate messages requiring a reply to a command. This allows more than one command to be sent to a device without waiting for a Reply Notification cell, as the field is copied from the Command cell to the Reply Notification cell. The 2-byte field is set to zero when an Event Notification cell is generated by the 77V011, with the zero value being valid for this condition only. It is up to the CPU to generate and manage values for it's In-StreamTM commands and not re-use the value for some set amount of time.
Byte 8 contains the Message Type field, which indicates what type of command the cell contains. Bit location eight is not used. Bit seven is the Acknowledge Request bit, which indicates if an acknowledgement to the command cell is required or not. When a Reply Notification cell has to be returned this bit is set to a one. When the Reply Notification cell is returned the bit is reset to zero by the 77V011. This option is not valid with the Reset command, which does not return a Reply Notification cell. Bit six is the Acknowledge bit which indicates whether the cell is a Reply Notification cell or a Command cell. This bit is set to a zero when the cell is a Command cell, and is set to a one, by the 77V011, when the cell is a Reply Notification cell. Bits one thorough five are the Message Type Indicator. There are currently five commands for this field. The Discover/Identify (value = 0x2) command, which will generate a Reply Notification cell with 32 bytes of device specific data located in the Message Data field. The Reset (value = 0x3) command performs a reset on the 77V011. There is no Reply Notification cell returned for this command. The Read Registers (value = 0x5) command performs a read operation to a set of consecutive registers. The returned register data is contained in the Message Data field. The Write Registers (value = 0x6) command performs a write operation to a set of consecutive registers. The data to be written is contained in the Message Data field. The Event Notification (value = 0x8) command generates a Event Notification cell indicating that an interrupt has been detected. Bytes 9 thorough 15 are the Device ID field. There are two formats to this field depending on the type of command the cell carries. When the cell contains either the Register Read/Write, or Event Notification command this field must contain a value of 0x01 in byte location 9 to be valid. The remaining six bytes are not used and should contain zeros. When the cell contains the Discovery/Identify command this field contains data from the EEPROM, with data from EEPROM byte location 8 being written to the first byte position of this field. Bytes 16 thorough 51 are the Message Data field. The layout of this field is dependant on the Message Type field. A Read or Write command will have a Message Data field divided into three sub fields. The first sub field is one byte wide and indicates how many bytes of data are valid in the data portion of the Message Data field. The second sub field is three bytes wide and contains the base address for the Read or Write command. The third sub field is the valid data and padding. Valid data is written starting at the base address in accordance with the number of valid bytes indicator (first sub field). The remaining space, if any, is padded with zeros. A Discover/Identify command has a Message Data field divided into two sub fields.The first sub field is the first 25bytes of the Message Data field, which contains up to 25 bytes read from the EEPROM, starting at EEPROM byte location 15. The remaining bytes are reserved. An Event Notification command will have a Message Data field split into two sub fields. The first sub field is two bytes wide and contains an event number, which is always 0x0100. The second sub field contains one byte of data (byte 18) indicating what type of event happened, which is described in the Event Notification Table. The remaining bytes 19 to 51 are padding and contain zeros. Bytes 52 and 53 contain the CRC-10 trailer, with the upper six bits of byte 52 containing zeros. The CRC-10 is generated and used in the same manner as in AAL3/4 cells.
JQLPPDUJRU3 PDHUW6Q, JQLPPDUJRU3 PDHUW6Q, JQLPPDUJRU3 PDHUW6Q, JQLPPDUJRU3 PDHUW6Q,
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IDT77V011
In-StreamTM Cell Header Byte 0 In-StreamTM Cell Header Byte 1 In-StreamTM Cell Header Byte 2 In-StreamTM Cell Header Byte 3
800F 8010 8011 8012
[7:0] [7:0] [7:0] [7:0]
In-StreamTM Header [31:24] In-StreamTM Header [23:16] In-StreamTM Header [15:8] In-StreamTM Header [7:0]
0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF
0x00 0x00 0x01 0xF2
Cell header used for In-StreamTM programming cells. Cell header used for In-StreamTM programming cells. Cell header used for In-StreamTM programming cells. Cell header used for In-StreamTM programming cells.
Table 18 In-StreamTM Register Table
Discover/ Identify Reset Read Registers Write Registers
2 3 5 6
This command will generate an Acknowledge Reply cell containing 32 bytes of device specific data, which is stored in bytes 8 through 39 of the EEPROM. Performs a reset on 77V011 device. No Reply Notification Cell is returned acknowledging that the reset command has been completed. Read from a consecutive number of registers. Write to a consecutive number of registers. An unsolicited Event Notification cell indicating an event has taken place. The event can be either a PHY interrupt or a Address Range Error. Table 19 In-Stream TM Programming Message Type Indicator
Event Notification 8
0 1 2 3 7:4
PHY Interrupt Time Out PHY Interrupt Status Address Range Error Time Out Address Range Error Status Not Used
A PHY interrupt was detected more than 25ms ago, but the PHY Interrupt bit of the Status register has not been cleared. A PHY interrupt has been detected. An address range error was detected more than 25ms ago, but the Address Range Error bit of the Status register has not been cleared. An address range error has been detected.
Table 20 Event Notification Table
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HPD1 UHWVLJH5 HPD1 WL%
IDT77V011
byte 1 ATM Header byte 5 byte 6 byte 7 byte 8 byte 9 Device ID byte 15 byte 16 Message Data and/or Padding Transaction ID Message Type
byte 51 byte 52
Trailer byte 53
5348drw21
Figure 20 General Format In-StreamTM Programming Cell Format
UNI Cell Header (five byte field) Bit 8 7 GFC VPI VCI VCI HEC PT CLP 6 5 4 3 VPI VCI 2 1 1 2 VPI 8 7 6 5 VPI VCI VCI VCI HEC PT CLP NNI Cell Header (five byte field) Bit 4 3 2 1 1 2 3 4 5
5348drw23
Byte
3 4 5
5348drw22
Figure 21 Valid Header Formats for In-StreamTM Programming Cell
Command Cell Transaction ID (two byte field) Bit 8 7 6 5 4 3 2 1 8 7
0 0
Notification Cell Transaction ID (two byte field) Bit 6
0 0
5
0 0
4
0 0
3
0 0
2
0 0
1
Byte
Copied from Command Cell
7
0
0
7
5348drw24
Figure 22 Valid Transaction Field Formats for In-Stream TM Programming Cell
Message Type (one byte field) Bit 8 7 6 5 4 3 2 1 8
Message Type ID Acknowledge Bit Acknowledge Request Bit Not Used
5348drw25
Figure 23 Valid Message Type Format for In-StreamTM Programming Cell
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Byte
March 15, 2001
Byte
Copied from Command Cell
6
0
0
6
Byte
IDT77V011
Device ID (seven byte field) Bit 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 8 1 9 Data from EEPROM Not Used Not Used Not Used Not Used Not Used Not Used 10 10 11 12 13 14 14 15 Data from EEPROM
5348drw26 5348drw26a
Discovery/Identify Command Cell Device ID (seven byte field) Bit 7 6 5 4 3 2 1 9
13
15
Figure 24 Valid Device ID Field Format for In-StreamTM Programming Cell
Read/Write Command Cell Message Data and/or Paddind Field (36 byte field) Bit 8 7 6 5 4 3 2 1 16 17 18 8 7 6 5 Notification Command Cell Message Data and/or Paddind Field (36 byte field) Bit 4 3 2 1 16 17 18
Number of valid bytes Base address Base address Base address Data and/or padding
Event number Event number Data and/or padding
Byte
19 20
Data and/or padding
51
5348drw27
Data and/or padding
51
5348drw28
Discover/Identify Command Cell Message Data and/or Paddind Field (36 byte field) Bit 8 7 6 5 4 3 2 1 16
Data from EEPROM
Reserved
41
Reserved
51
5348drw29
Figure 25 Valid Message
and/or Data Field Format for In-StreamTM Programming
Byte
Data from EEPROM
40
Cell
Trailer (two byte field) Bit 8
0
7
0
6
0
5
0
4
0
3
0
2
1
CRC10
53
Byte
CRC10
52
5348drw30
Figure 26 Valid Trailer Field Format for In-Stream TM Programming Cell
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Byte
Byte
12
Byte
11
IDT77V011
There are two types of Notification cells, Event and Reply, that can be generated by the 77V011. The 77V011 will generate an Event Notification Cell if an interrupt is detected on the external PHYINT pin, or if an Address Range Error is encountered. A second Event Notification cell will be generated if the interrupt is not cleared within 25ms of when it occurred. Additional Event Notification cells will be generated every 12ms thereafter until the interrupt is cleared. A new event will not be reported until the related interrupt has been cleared. It is up to the CPU to clear the interrupt, or to notify higher layers that an interrupt has occurred. The interrupts are cleared by writing a one to the PHY Interrupt or Address Range Error bits in the Status register. Writing a one will clear the interrupt and reset the register bit to zero. The 77V011 will generate a Reply Notification cell if the Acknowledge Request bit is set to a one. Reply Notification cells enable the CPU to keep status of its command cells.
The PHY Interrupt Status and Address Error Status bits of the Timeout Status register indicate that the interrupt occurred more than 25ms ago. This is a read only register used to verify that the interrupts are being cleared by the CPU. Once an interrupt is detected the 77V011 will monitor the appropriate Status register bit to determine if the interrupt is cleared. The 77V011 will generate a Event Notification cell, mask bit must be set to a one, if the interrupt is not cleared within 25ms of when the interrupt occurred and will set the Timeout Status bit. It will generate additional Event Notification cells on 12ms intervals, thereafter, until the interrupt is cleared. It is the CPU's responsibility to clear the interrupt and/or notify higher layers that an interrupt has been encountered. The interrupt is cleared by the CPU writing a one to the appropriate Status register bit. Writing a one will clear the interrupt and reset the register bit back to zero. See Interrupt Register Table for description of interrupt registers.
When an interrupt occurs the Status register will indicate where the interrupt occurred. The PHY Interrupt Mask and Rx Address Error bits of the Notification Mask register determine if a Event Notification cell will be generated when an interrupt is detected. The 77V011 will not generate a Event Notification cell when an interrupt occurs if the register is set to the default of zero, and will generate a Event Notification cell if set to a one. The Tx Cell Drop bit of the Status register must be polled by the CPU to determine if it is set or not set. An Event Notification cell is not generated when this bit is set, and no action needs to be taken by the CPU. However, the bit must be cleared, by writing a zero to it, in order to detect additional cells that have been dropped.
The transmit and receive cell counters are always enabled. At reset the counters are set to zero and will increment by one each time a cell is received or transmitted over the UTOPIA interface. The counter values are stored in the UTOPIA Tx and Rx Cell Counter registers and can be read at any time. The counters will roll over once the maximum cell count is reached.
The 77V011 offers two external control pins, CNTRL_A and CNTRL_B, that can be connected to an external device for system design engineer usage. Both of these signals are low after reset. There is also a register associated with each control pin signal, which is described in the Misc. Register Table.
Notification Mask Status Timeout Status
8008
0
PHY Interrupt Mask PHY Interrupt PHY Interrupt Status
0-1
0
Mask interrupt notification. "0" no Event Notification cell will be generated when a PHY interrupt occurs, "1" generate Event Notification cell when a PHY interrupt occurs. When a interrupt occurs on the PHYINT pin this bit will be set to a one. "0" no interrupt detected, "1" PHY interrupt detected. Indicates that a PHY interrupt occurred more than 25ms ago, and the PHY Interrupt bit of the Status register has not been cleared. This bit will return to zero once the interrupt is cleared. "0" no PHY interrupt detected, "1" interrupt occurred more than 25ms ago and has not been cleared.
8009 800A
0 0
0-1 0-1
0 0
Table 21 Interrupt Register Table
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VVHUGG$ HPD1 UHWVLJH5 UHWVLJH5
March 15, 2001
IDT77V011
UTOPIA Rx Cell Counter byte 3 UTOPIA Rx Cell Counter byte 2 UTOPIA Rx Cell Counter byte 1 UTOPIA Rx Cell Counter byte 0 UTOPIA Tx Cell Counter byte 3 UTOPIA Tx Cell Counter byte 2 UTOPIA Tx Cell Counter byte 1 UTOPIA Tx Cell Counter byte 0
801B 801C 801D 801E 801F 8020 8021 8022
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]
Rx Cell Counter [31:24] Rx Cell Counter [23:16] Rx Cell Counter [15:8] Rx Cell Counter [7:0] Tx Cell Counter [31:24] Tx Cell Counter [23:16] Tx Cell Counter [15:8] Tx Cell Counter [7:0]
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Counter for cells transferred on the receive UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the receive UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the receive UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the receive UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached.
Table 22 Cell Counter Register Table
Pin Controls
801A
1 2
Control A Control B
0-1 0-1
0 0
Stores condition of Control A pin. "0" CNTRL_A = "0", "1" CNTRL_A = "1". Stores condition of Control B pin. "0" CNTRL_B = "0", "1" CNTRL_B = "1".
Table 23 Misc.+ Register Table
tCYC tCH tCL tUCYC tUCH tUCL tTOV tUTS tUTH tROV tURS tURH
SYSCLK Cycle Time SYSCLK High Time SYSCLK Low Time UTOPIA TCLK/RCLK Cycle Time UTOPIA TCLK/RCLK High Time UTOPIA TCLK/RCLK Low Time TxDATA, TENB, TSOC Output Valid from TCLK TCLAV to TCLK Setup Time TCLAV to TCLK Hold Time RENB Output Valid from RCLK RxDATA, RSOC, RCLAV to RCLK Setup Time RxDATA, RSOC, RCLAV to RCLK Hold Time
20 8 8 25 10 10 2 4 1 -- 10 1
-- -- -- -- -- -- 20 -- -- 20 -- --
ns ns ns ns ns ns ns ns ns ns ns ns
Table 24 AC Electrical Characteristics (Industrial: Vcc = 5V 10%, TA = -40C the 85C (Part 1 of 3)
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WLQ8
QRLWSLUFVH'
[D0
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VHXOD9 WOXDIH' VHXOD9 HJQD5
UHWHPDUD3
HPD1 WL% HPD1 WL%
QRLWDFR/ ;(+ WL% VVH UGG$ WL% VVHUGG$ UHWVLJH5
OREP\6
HPD1 UHWVLJH5 HPD1 UHWVLJH5
IDT77V011
tDCYC tDCH tDCL tDTS tDTH tPDRD tALPW tALR tALW tRDPW tAAL tALA tDRS tDRH tDWS tDWH tWRPW tPINTS tPINTH tAW tPALE tPPHY tPPHYR tPRCLK tPTCLK tPDRxCLK tPDTxCLK tPRLED tPTLED tPCNTA tPCNTB tRSTW tECYC tPECLK tSEDI tHEDI
DPI DTxCLK/DRxCLK Cycle Time DPI DTxCLK/DRxCLK High Time DPI DTxCLK/DRxCLK Low Time DTxFRM, DTxDATA to DTCLK Setup Time DTxFRM, DTxDATA to DTCLK Hold Time DRxCLK to DRxDATA(0-3), DRxFRM Propagation Delay ALE Pulse Width System Clock to READ Low Propagation Delay System Clock to WRITE Low Propagation Delay Read Pulse Width Address to ALE Falling Edge Setup Time Address to ALE Falling Edge Hold Time Data to rising edge of READ Setup Time Data to rising edge of READ Hold Time Data to rising edge of WRITE Setup Time Data to rising edge of WRITE Hold Time Write Pulse Width System Clock to PHYINT Setup Time System Clock to PHYINT Hold Time ALE falling edge to WR falling edge ALE to System Clock Propagation Delay System Clock to PHYCS Propagation Delay System Clock to PHYRST Propagation Delay System Clock to Utopia Receive Clock Propagation Delay System Clock to Utopia Transmit Clock Propagation Delay System Clock to DPI Receive Clock Propagation Delay System Clock to DPI Transmit Clock Propagation Delay System Clock to RxLED Propagation delay System Clock to TxLED Propagation delay System Clock to CONT_A Propagation delay System Clock to CONT_B Propagation delay SYSRST pulse width EECLK Cycle Time SYSCLK to EECLK, EECS, EEDOUT Propagation Delay SYSCLK to EEDIN Setup Time SYSCLK to EEDIN Hold Time
20 8 8 4 2 -- 20 -- -- 80 20 10 5 1 5 1 40 10 1 25 -- -- -- -- -- -- -- -- -- -- -- 100 1000 -- -- 2
-- -- -- -- -- 10 -- 20 20 -- -- -- -- -- -- -- -- -- -- -- 20 20 20 20 20 20 20 20 20 20 20 -- -- 20 10 --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 24 AC Electrical Characteristics (Industrial: Vcc = 5V 10%, TA = -40C the 85C (Part 2 of 3)
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WLQ8
[D0
QL0
UHWHPDUD3
OREP\6
IDT77V011
tADRS tADRH tSELRS tSELRH tDARIV tDARV tRDYRV tRDYRT tRDPW tRDYWV tRDYWT tADWS tSELWS tSELWH tDAWS tDAWH tWRPW
ADDR to RD/DS Falling Edge Setup Time ADDR to RD/DS Rising Edge Hold Time SEL to RD/DS Falling Edge Setup Time SEL to RD/DS Rising Edge Hold Time DATA Invalid/Tri-state to RD/DS Rising Edge DATA Valid to RDY/DTACK Falling Edge RDY/DTACK Valid to RD/DS Falling Edge RDY/DTACK Tri-state to RD/DS Rising Edge RD/DS Pulse Width RDY/DTACK to WR/RW Falling Edge RDY/DTACK Tri-state to WR/RW Rising Edge ADDR to WR/RW Falling Edge Setup Time SEL to WR/RW Falling Edge Setup Time SEL to WR/RW Rising Edge Hold Time DATA to WR/RW Rising Edge Setup Time ADDR, DATA to WR/RW Rising Edge Hold Time WR/RW Pulse Width
10 4 5 0 15 -- -- 10 50 -- -- 15 5 0 15 4 50
-- -- -- -- -- 10 15 -- -- 15 10 -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 24 AC Electrical Characteristics (Industrial: Vcc = 5V 10%, TA = -40C the 85C (Part 3 of 3)
tCYC SYSCLK tCH tCL
5348drw31
Figure 27 System Clock Timing Waveform
SYSCLK tPRCLK RCLK
5348drw32
Figure 28 System Clock to UTOPIA Receive Clock Propagation Delay
SYSCLK tPTCLK TCLK
5348drw33
Figure 29 System Clock to UTOPIA Transmit Clock Propagation Delay
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[D0
QL0
UHWHPDUD3
OREP\6
IDT77V011
SYSCLK tPDRxCLK DRxCLK
5348drw34
Figure 30 System Clock to DPI Receive Clock Propagation Delay
SYSCLK tPDTxCLK DTxCLK
5348drw35
Figure 31 System Clock to DPI Transmit Clock Propagation Delay
tUCYC TCLK tUCH tTOV TxDATA(0-7), TENB, TSOC tUTS TCLAV
5348drw36
tUCL
tUTH
Figure 32 UTOPIA Transmit Timing Waveform
RCLK tROV RENB tURS tURH
RxDATA(0-7), RSOC, RCLAV
5348drw37
Figure 33 UTOPIA Receive Timing Waveform
tDCYC DTxCLK tDCH tDCL tDTS DTxFRM, DTxDATA(0-3)
5348drw38
tDTH
Figure 34 DPI Transmit Timing Waveform
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IDT77V011
DRxCLK
tPDRD DRxFRM, DRxDATA(0-3)
5348drw39
Figure 35 DPI Receive Timing Waveform
SYSCLK
tPPHYR
P H Y R ST
5348drw40
Figure 36 System Clock to PHYRST Propagation Delay
SYSCLK
tPINTS tPINTH
PHYINT
5348drw41
Figure 37 System Clock to PHYINT Propagation Delay
tRSTW
SYSRST
5348drw42
Figure 38 SYSRST Timing Waveform
tPECLK SYSCLK
EECS
EECLK EEDO tSEDI EEDI
5348drw43
tHEDI
Figure 39 EEPROM Timing Waveform
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IDT77V011
Device ID Configuration 1
8000 8001
[7:0] 0 1
Device Version Number Drop Tx Cell Copy EFCI
0x10 0 0
This is the device version number. 77V011 = 0x10. "Selects whether or not to drop cell with invalid Subport Address. "0" do not drop the cell, "1" drop the cell." "Selects whether or not to OR the EFCI bit of the cell header with the EFCI bit of the 4-byte TAG area appended to the beginning of the cell, and place the OR'ed EFCI bit in the cell header. This option is not valid when the TAG is appended to the end of the cell. "0" do not OR the EFCI bit to the 4-byte TAG area, "1" OR the EFCI bit to the 4-byte TAG area." "Selects whether or not to move the PT/CLP fields from the cell header into the 4-byte TAG area appended to the beginning of the cell. This option is not valid when the TAG is appended to the end of the cell. "0" do not move the PT/CLP to the 4-byte TAG area, "1" move the PT/CLP to the 4-byte TAG area. " "Selects whether or not to move the PT/CLP fields from the 4-byte TAG area appended to the beginning of the cell into the cell header. This option is not valid when the TAG is appended to the end of the cell. "0" do not move the PT/CLP fields to the cell header, "1" move the PT/CLP fields to the cell header."
2
Rx Move PT/ CLP
0
3
Tx Move PT/CLP 0
[7:4] Configuration 2 8002 [1:0]
Not Used Stall Tx 0x0 "Selects whether or not to stall the pipeline if the PHY transmit FIFO is full. "0" drop the cell, "1" stall the pipeline indefinitely, "2" stall the pipeline for Stall Cycles." Indicates the maximum subport address value for the PHY(s) connected to the transmit UTOPIA II interface.
[6:2] 7 Configuration 3 8003 [7:0]
Max Subports Not Used Stall Tx Cycles
0x1E
0xFF
Number of TCLK cycles the interface has to stall the pipeline when the PHY transmit FIFO is full. This field is valid only if the Stall Pipeline for Stall Cycles option is selected. Number of bytes to remove from the ATM cell in the transmit direction. Valid values are from zero to four. "Add a HEC placeholder in the transmit direction. "0" do not add a HEC placeholder, "1" add a HEC placeholder." "TAG location in transmit direction. "0" transmit TAG is located at the beginning of the cell, "1" transmit TAG is located at the end of the cell."
Tx TAG
8004
[2:0] 3 4
Tx TAG Size Tx Add HEC
Defined by pin Defined by pin
Tx TAG Location Defined by pin [7:5] Not Used Defined by pin
Rx TAG
8005
[2:0] 3 4
Rx TAG Size
Number of bytes to add to ATM cell in the receive direction. Valid values are from zero to four. "Remove HEC byte from cell. "0" do not remove the HEC byte from the cell, "1" remove the HEC byte from the cell." "TAG location in receive direction. "0" receive TAG is located at the beginning of the cell, "1" receive TAG is located at the end of the cell."
Rx Remove HEC Defined by pin Rx TAG Location Defined by pin [7:5] Not Used
Table 25 Internal Register Map (Part 1 of 4)
38 of 43
QRLWSLUFVH'
March 15, 2001
HXOD9 WOXDIH' HPD1 WL%
QRLWDFR/ ;(+ WL% VVHUGG$ HPD1 UHWVLJH5
SD0 UHWVLJH5 ODQ UHWQ, SD0 UHWVLJH5 ODQ UHWQ, SD0 UHWVLJH5 ODQ UHWQ, SD0 UHWVLJH5 ODQ UHWQ,
IDT77V011
Mode Select
8006
0 1 2 3 4
Dpi Size Dpi Mode UTOPIA 2 Size UTOPIA Management Mode Init from EEPROM Not Used PHY Reset Not Used PHY Interrupt Mask
Defined by pin Defined by pin Defined by pin Defined by pin Defined by pin
"Selects the size of the DPI Tx and Rx data bus. "0" 4-bit DPI Tx and Rx data bus, "1" 8-bit DPI Tx and Rx data bus." "Selects DRxCLK direction. "0" switch mode (output), "1" normal mode (input)." "Selects the size of the UTOPIA 2 Tx and Rx data bus. "0" 8-bit UTOPIA 2 Tx and Rx data bus, "1" 16-bit UTOPIA 2 Tx and Rx data bus." "Selects type of management interface to use. "0" Utility bus style, "1" UTOPIA 2 management style." "Five byte write from EEPROM to In-StreamTM Cell Header and In-StreamTM Subport registers at reset. "0" do not write five byte value, "1" write five byte value to registers."
[7:5] PHY Reset 8007 0 [7:1] Notification Mask 8008 0
0
"PHY Reset. "0" do not reset the PHY, "1" reset the PHY(PHYRST signal will be asserted low for at least 16 SYSCLK cycles."
0
"Mask interrupt notification. "0" no Event Notification cell will be generated when a PHY interrupt occurs, "1" generate Event Notification cell when a PHY interrupt occurs." "Mask Address Range Error notification. "0" no Event Notification cell will be generated when a Rx Out of Range Address Error occurs, "1" generate Event Notification cell when a Rx Out of Range Address Error occurs."
1
Rx Address Error 0
[7:2] Status 8009 0 1
Not Used PHY Interrupt Address Range Error 0 0 "When a PHY interrupt occurs on the external PHY interrupt pin this bit will be set high. "0" no interrupt detected, "1" PHY interrupt detected." "Address Range Error indication when an Address Range Error occurs. "0" no Address Range Error detected, "1" Address Range Error has been detected." "Indicates if any cells have been dropped at the transmit UTOPIA interface. This is a status indicator for the Stall Tx bit of the Configuration 2 register "0" no cells have been dropped, "1" a cell was dropped because the PHY did not respond."
2
Tx Cell Dropped 0
[7:3] Timeout Status 800A 0
Not Used PHY Interrupt Status 0 "Indicates that a PHY interrupt occurred more than 25ms ago, and the PHY Interrupt bit of the Status register has not been cleared. This bit will return to zero once the interrupt is cleared. "0" no PHY interrupt detected, "1" interrupt occurred more than 25ms ago and has not been cleared." "Indicates that a Address Error occurred more than 25ms ago, and Address Range Error bit of the Status register has not been cleared. This bit will return to zero once the interrupt is cleared. "0" no Address Range Errors detected, "1" Address Range Error occurred more than 25ms ago and has not been cleared."
1
Address Error Status
0
[7:2]
Not Used Table 25 Internal Register Map (Part 2 of 4)
39 of 43
QRLWSLUFVH'
March 15, 2001
HXOD9 WOXDIH' HPD1 WL%
QRLWDFR/ ;(+ WL% VVHUGG$ HPD1 UHWVLJH5
IDT77V011
Rx Out of Range Subport
800B
[4:0] [7:5]
Rx Out of Range 0x00 Subport Not Used Address Mask 0x00 Register [23:16] Address Mask Register [15:8] Address Mask Register [7:0] In-StreamTM Header [31:24] In-StreamTM Header [23:16] In-StreamTM Header [15:8] In-StreamTM Header [7:0] In-StreamTM Subport Tx Subport Width New Subport 0x00 0x00 0x00 0x00 0x01 0xF2 0x00 0x5 0x00
The subport address of a cell containing an invalid cell header.
Rx Out of Range Address Mask byte 2 Rx Out of Range Address Mask byte 1 Rx Out of Range Address Mask byte 0 In-StreamTM Cell Header byte 3 In-StreamTM Cell Header byte 2 In-StreamTM Cell Header byte 1 In-StreamTM Cell Header byte 0 Subport Configuration 1
801C 800D 800E 800F 8010 8011 8012 8013
[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [4:0] [7:5]
Value used to validate cells on the Rx UTOPIA interface. Value used to validate cells on the Rx UTOPIA interface. Value used to validate cells on the Rx UTOPIA interface. Cell header used for In-StreamTM programming cells. Cell header used for In-StreamTM programming cells. Cell header used for In-StreamTM programming cells. Cell header used for In-StreamTM programming cells. Subport address used to filter In-StreamTM programming cells. Programs how many bits will be used for subport addressing in the transmit direction. New value used to replace subport address in outgoing cells. This value will only be used if the Replace Subport bit of the Modify Tx Subport register is set to a one. "Indicates whether or not to replace the subport address in transmit cells. "0" do not replace the subport address, "1" replace the subport address with the value in the New Subport bits of the Modify Tx Subport register."
Modify Tx Subport
8014
[4:0]
5
Replace Subport 0
[7:6] Tx Subport Position 8015 [2:0] [5:3]
Not Used Tx Byte Location Defined by pin Tx Bit Location 0x5 Indicates what byte of the transmit cell header the subport starts in. The subport address can cross the byte boundary. Indicates what bit of the byte defined by the Tx Byte Location bits of the Tx Subport Position register the MSB of the transmit subport address starts. The subport address can cross the byte boundary.
[7:6] TAG byte 3 TAG byte 2 TAG byte 1 TAG byte 0 8016 8017 8018 8019 [7:0] [7:0] [7:0] [7:0]
Not Used TAG [31:24] TAG [23:16] TAG [17:8] TAG [7:0] 0x00 0x00 0x00 0x00 TAG added to cell. TAG added to cell. TAG added to cell. TAG added to cell.
Table 25 Internal Register Map (Part 3 of 4)
40 of 43
QRLWSLUFVH'
March 15, 2001
HXOD9 WOXDIH' HPD1 WL%
QRLWDFR/ ;(+ WL% VVHUGG$ HPD1 UHWVLJH5
IDT77V011
Pin Controls
801A
0
Override Pin Configuration Control A Control B EEPROM Mux Select
0
"Enables writing to pin configurable registers during normal operation. "0" pin configurable registers are read only, "1" pin configurable registers are read/write registers." "Stores condition of Control A pin. "0" CNTRL_A = "0", "1" CNTRL_A = "1"." "Stores condition of Control B pin. "0" CNTRL_B = "0", "1" CNTRL_B = "1"." "Indicates if the EEPROM interface will be connected to the internal logic or the EEPROM registers. "0" connected to internal logic, "1" connected to EEPROM registers." "EEPROM clock when EEPROM interface is connected to the EEPROM registers. "0" clock low, "1" clock high." "EEPROM chip select when EEPROM interface is connected to the EEPROM registers. "0" EEPROM interface is selected, "1" EEPROM interface is not selected." EEPROM serial output when EEPROM interface is connected to the EEPROM registers. EEPROM serial input when EEPROM interface is connected to the EEPROM registers. Counter for cells transferred on the receive UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the receive UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the receive UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the receive UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will wrap around once the maximum cell count is reached. Programs how many bits will be used for subport addressing in the receive direction.
1 2 3
0 0 0
4 5
EEPROM Clock 0 Out EEPROM Chip Select EEPROM Out EEPROM In 0
6 7 UTOPIA Rx Cell Counter byte 3 UTOPIA Rx Cell Counter byte 2 UTOPIA Rx Cell Counter byte 1 UTOPIA Rx Cell Counter byte 0 UTOPIA Tx Cell Counter byte 3 UTOPIA Tx Cell Counter byte 2 UTOPIA Tx Cell Counter byte 1 UTOPIA Tx Cell Counter byte 0 Subport Configuration 2 801B 801C 801D 801E 801F 8020 8021 8022 8023 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [2:0] [7:3] Rx Subport Position 8024 [2:0] [5:3]
0 0
Rx Cell Counter 0x00 [31:24] Rx Cell Counter 0x00 [23:16] Rx Cell Counter 0x00 [15:8] Rx Cell Counter 0x00 [7:0] Tx Cell Counter [31:24] Tx Cell Counter [23:16] Tx Cell Counter [15:8] Tx Cell Counter [7:0] Rx Subport Width Not Used Rx Byte Location Defined by pin Rx Bit Location 0x5 0x00 0x00 0x00 0x00 0x5
Indicates what byte of the receive cell header the subport starts in. The subport address can cross the byte boundary. Indicates what bit of the byte defined by the Rx Byte Location bits of the Rx Subport Position register the MSB of the receive subport address starts. The subport address can cross the byte boundary.
[7:6]
Not Used Table 25 Internal Register Map (Part 4 of 4)
41 of 43
QRLWSLUFVH'
March 15, 2001
HXOD9 WOXDIH' HPD1 WL%
QRLWDFR/ ;(+ WL% VVHUGG$ HPD1 UHWVLJH5
IDT77V011
Plastic QFP 144pin Body size 20 x 20 x 1.4mm
HD D
108 73
A2
Amax
A1
Min 19.9 19.9
Norm
Max
Min (0.784) (0.784)
Norm
E D A A1 A2 f b C L L1 L2 HE HD 2 3 R R1
1. for reference
20 20 0.1
20.1 20.1 1.7
(0.787) (0.787) (0.004)
1.3 0.15 0.1 0o 0.3
1.4 0.5 0.2 0.125 0.5 1 0.5
1.5 0.3 0.175 10o 0.7
(0.052) (0.006) (0.004) (0o) (0.012)
(0.055) (0.020) (0.008) (0.005) (0.020) (0.039) (0.020)
21.6 21.6
22 22 12o 12o 0.2 0.2
22.4 22.4
(0.851) (0.851)
(0.866) (0.866) (12o) (12o) (0.008) (0.008)
42 of 43
VHKFQ,
QL QRLVQHPL'
VUHWHPLOOL0 QL QRLVQHPL'
QRLWDPURIQ, HJDNFD3 QRLWDPURIQ, HJDNFD3 QRLWDPURIQ, HJDNFD3 QRLWDPURIQ, HJDNFD3
109 f b 144
72
E
HE
Index 37
1
36
2
R1 R
3 L2 L1 L C
5348drw44
OREP\6
Max
(0.791) (0.791) (0.066) (0.059) (0.011) (0.006) (10o) (0.027)
(0.881) (0.881)
March 15, 2001
IDT77V011
\ URWVL+ WQHPXFR' WHHKVDWD' \ URWVL+ WQHPXFR' WHHKVDWD' \ URWVL+ WQHPXFR' WHHKVDWD' \ URWVL+ WQHPXFR' WHHKVDWD'
QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2 QRLWDP URIQ, JQLUHGU2
IDT XXXXX Device Type A 999 Power Speed
A Package
A Process/ Temperature Range
(Blank) Industrial
DA
PQFP (144-pin)
155
4-bit Port Bandwidth in Mbps
L
Low Power
77V011 DATA PATH INTERFACE (DPI) TO UTOPIA LEVEL 1 HEADER TRANSLATION DEVICE
5348drw45
9/28/99
Initial Public Release
01/17/00 02/03/00 03/03/00 05/15/00 09/12/00 10/01/00 1218/00
Corrected package type from DX to DA in Ordering Information, corrected typo SCLK to SYSCLK in AC Electrical Characteristics, corrected sales and tech support phone numbers. Fixed typos in In-StreamTM text. Deleted commercial temperature range and ordering information, changed bandwidth chart to reflect maximum values, updated Utilit y bus write timing. Corrected table 5348tbl15 8-bit UTOPIA to 8-bit DPI conversion. Corrected In-StreamTM data field description and drawing for Notification cells, moved Copy EFCI description from Receive Tag to Transmit Tag section. Changed default In-StreamTM header value from 0x1f0 to 0x1f2. Corrected register descriptions and text for Copy EFCI, Rx Move PT/ LP, and Tx C Move PT/CLP. Added drawing 5248drw26a and corrected text for Discover/Identify command. Changed In-StreamTM text for Read/ Write command from 32bytes to 31-bytes. Corrected Register Address Map drawing 5348drw18. Added Subport text to In-StreamTM header detection text. Changed default TAG byte 0 and 1 to 0x00. Removed TAG byte 0, 1, 2, and 3 from table 5348tbl28. Changed from Preliminary to Final. In Pin Configuration Diagram, CTRL_B changed from Pin 53 to Pin 52 and CTRL_A changed from Pin 52 to Pin 53. In AC Electrical Characteristics Table, changed TUTH from 10ns to 1ns.
3/15/01
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com
for Tech Support: email: sarhelp@idt.com phone: 408-492-8208
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
43 of 43
March 15, 2001

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